Modified Project Oberon for SDRAM and DDRAM Interface

Modified Project Oberon for SDRAM and DDRAM Interface

Details

Category: System on Chip

Created: February 10, 2017

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Stable

WishBone compliant: No

WishBone version: n/a

License: LGPL

Description

Project Oberon http://www.projectoberon.com modified to use SDRAM instead of static RAM
Static RAM is old technology in FPGA world, and 1MB 32bit SRAM is hard to find on FPGA dev boards.
I upgraded this great project with a cache memory, which is able to interface SDRAM and DDRAM.
I uploaded the project archives for FleaFpga and for PapilioPro.
I will also provide DE2-115 and Nexys4 versions.