STORM SoC (System on Chip) with 32-bit Wishbone Bus System

STORM SoC (System on Chip) with 32-bit Wishbone Bus System

Details

Category: System on Chip

Created: February 17, 2012

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Beta

Additional info: FPGA proven

WishBone compliant: Yes

WishBone version: n/a

License: GPL

Description

Welcome to the STORM SoC project!

This is an FPGA/evaluation board-independent, complete system on chip implementation based on the STORM CORE processor.
Most of the SoC's components were designed by myself, but the are also some IPs used, which are available here at oppencores.
All components are connected via an 32-bit, pipelined Wishbone bus fabric.

The boot ROM features a pre-installed bootloader, which allows easy program downloading to RAM or to an attached I²C EEPROM.
It is also capable of booting program files directly from the EEPROM.
Compatible programs files can be generated by using the provided WinARM-compatible makefiles.
Included IO driver libraries allow fast and easy program setup.
A tutorial shows how to extend the hardware platform with own IP cores.


,
,STORM Core Processor project page,
,
,
,STORM SoC features (basic configuration):,
,

  • FPGA independent microcontoller-like system on chip based on the STORM CORE Processor
  • Opcode and function compatible to ARM's 32-bit instruction set processor series (ARMv2)
  • 1kb D- and 1kb I-cache (full associative)
  • 32-bit pipelined Wishbone bus system
  • Clock manager (PLL) and reset generator
  • WinARM compatible makefiles
  • Pre-defined IO driver libraries (C files)
  • Internal 32kb SRAM
  • Internal 8kb boot ROM with pre-installed bootloader
  • Supports booting from UART, RAM and attached I²C EEPROM
  • 32-bit system timer
  • Vector-interrupt-controller (LPC native)
  • General purspose IO pins (8xIN, 8xOUT)
  • I²C and SPI controller
  • Simple mini UART
  • 8 PWM outputs
  • Easy-to-extend hardware platform
  • Demo program included
  • Tutorial for system setup and modification
  • ...


,Implementation results of STORM SoC basic configuration:,
,

  • Target board: Altera/Terasic DE0nano board
  • Target FPGA: Altera Cyclone IV E EP4CE22F17C6
  • Total logic elements: 11,518 / 22,320 ( 52 % )
  • Total comb. functions: 11,158 / 22,320 ( 50 % )
  • Dedicated logic registers: 5,298 / 22,320 ( 24 % )
  • Embedded Multiplier 9-bit elements: 6 / 132 ( 5 % )
  • Total pins: 60 / 154 ( 39 % )
  • Total memory bits: 344,064 / 608,256 ( 57 % )
  • Totla PLLs: 1 / 4 ( 25 % )
  • Maximum clock speed (slow 1200mV 0C model): 67.48 MHz
  • Target board: Altera/Terasic DE2 board
  • Target FPGA: Altera Cyclone II EP2C35F672C6
  • Total logic elements: 11,469 / 33,216 ( 35 % )
  • Total comb. functions: 11,096 / 33,216 ( 33 % )
  • Dedicated logic registers: 5,254 / 33,216 ( 16 % )
  • Embedded Multiplier 9-bit elements: 6 / 70 ( 9 % )
  • Total pins: 60 / 475 ( 13 % )
  • Total memory bits: 344,064 / 483,840 ( 71 % )
  • Totla PLLs: 1 / 4 ( 25 % )
  • Maximum clock speed (slow model): 56.96 MHz


,

Contact

If you have any questions about the STORM Core / STORM SoC or if you want to give any kind of
feedback, feel free to drop me some lines... 😉

  • stnolting@gmail.com