Dynamic Vectorial Generator

Dynamic Vectorial Generator


Category: Uncategorized

Created: March 22, 2013

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Stable

Additional info: Design done, FPGA proven

WishBone compliant: No

WishBone version: n/a

License: Others


Vectorial generator:

-Interface: bit or bus
-Configuration: dynamic
-Applications: waveform generator, serial or parallel communication


-Included in the own .vhd headfile


-It is necessary to adjust the following type which defines the input size (it affects to area resources):

SUBTYPE valores_vector IS INTEGER RANGE -1 TO nat_synth_65536'high; -- values range for each sample (always from -1)
TYPE vector_integer IS ARRAY (nat_synth_128'high DOWNTO 0) OF valores_vector; -- number of samples*2


SUBTYPE nat_synth_65536 IS NATURAL RANGE 0 TO 65535;
SUBTYPE nat_synth_2048 IS NATURAL RANGE 0 TO 2047;
SUBTYPE nat_synth_16 IS NATURAL RANGE 0 TO 15;