Baseline JPEG Encoder Codec Library Based on Microblaze
Category: Video Controller
Created: June 12, 2006
Updated: January 27, 2020
Other project properties
Development Status: Stable
Additional info: FPGA proven
WishBone compliant: No
WishBone version: n/a
- Baseline JPEG encoder
- Baseline JPEG decoder (Not ready yet)
This is an open source JPEG codec, including both encoder and decoder (decoder is not ready yet), for embedded systems. It can be fully synthesized and implemented on FPGA. There is also a four-processor design based on it http://opencores.orgproject,mpdma,mpdma20061023c.tar.bz2
Different to a fully hardware implementation, this JPEG codec is designed based on Xilinx Microblaze processor with customized hardware accelerators. It is expected to achieve high flexibility, low complexity at little cost of size and performance. We aim to archive real time motion JPEG codec on a Xilinx Spartan X3S1000 equivalent FPGA (including I/O and memory controller). **
You can open the project with Xilinx EDK7.1 or higher and synthesize by Xilinx ISE7.1. * The verification hardware platform I use is Xilinx XUP board with a Xilinx XC2V30P on it. It provides necessary peripherals such as CF card for image storage and video output. The board can be obtained at the cost of 300 euro if you are in a university. Simulation is not tested yet.
The code here includes two parts, a JPEG codec library and a test bench. The library includes both hardware and software. The test bench is to read a BMP file from CF card, drive JPEG code library to compress it and write the JPG file back to CF card. You can also make your own design to play with camera and video output based on it.
The JPEG codec library can also be used as a library or IP core for image processing and video compression applications, for instance, MPEG codec. The IP cores can be integrated immediately. It is actually part of my master thesis project and I try to write down in detail how I design and how to use it. Enjoy!
* Some intermediate version can only be open and synthesized by Xilinx EDK 8.1 and ISE 8.1, as indicated respectively.
** X3S1000: 1M Gates, 1920 CLBs, 432Kbits BRAM, Current implementation: 3460 CLBs, 589Kbits BRAM
*** Call for Participation ***
The accelerator is not done yet. It would be a nice project for university students or engineers who is interested in FPGA design. Please drop me an email if you like to join.
1. Setup the testbench and development environment
1.1 Simple environment with CF card and without external memory *
1.2 Full environment with CF card and external memory *
2. Port reference code to microblaze
2.1 Port code to XUP2PRO platform and microblaze processor *
2.2 Elaborate code for memory and platform independance *
2.3 Elaborate code for multiprocessor support
2.4 Elaborate code for multitask OS support
2.5 Elaborate code for speed
3. Design a simple FSL accelerator to evaluate the FSL design flow
3.1 Design a FSL accelerator for MAC operation *
4. Design DCT FSL accelerator
4.1 Update Fast DCT algorithm ( 4.2 Design Accelerator
5. Design color conversion accelerator
6. Design vlc accelerator
7. Port code into and optimize for different platforms
7.1 Port to Xilinx Spartan III board
7.2 Add Subsampling support *
8. Experiment for Motion JPEG streaming
9. Start to design MPEG codec... 😊
A project to design multiprocessor system on FPGA is based on this design. It can be found at http://opencores.orgproject,mpdma,overview
For decoder, it is roughly the same.
1. 2006/07/05 Step 1.1 - Setup the testbench and development environment/Simple environment with CF card and without external memory (Sunwei) CVSTag: STEP1_1 (EDK/ISE8.1)
2. 2006/07/18 Step 2.1 - Port reference code (Joris van Emden) to Microblaze and XUP2PRO board (Sunwei) CVSTag: STEP2_1b (EDK/ISE8.1)
You can download this bitstream to an Xilinx XUP2PRO board with CF card and it can compress image01.bmp on CF card to image01.jpg and write back to CF card. Due to current implementation limit, the BMP file size can not exceed 64KB for this version of bitstream. It is fixed later.
3. 2006/07/20 Step 3.1 - Design a FSL accelerator to do MAC operation (Sunwei) (EDK/ISE8.1)
4. 2006/07/28 Step 2.2 - Elaborate code for memory and platform independance.
The code is elaborated and memory usage is reduced. The code can also be compiled and run on PC without any modification. (Sunwei) CVSTag: STEP2_2b (EDK/ISE8.1)
The code size is reduced 30% and data size 50%. Now with the same capacity to V0.1 code it need only 32KB code and 32 KB data memory for microblaze processor on FPGA, compared to 64KB code plus 64KB data in V0.1 design. The software code is platform independant and can be compiled on PC as well.
5. 2006/09/15 Step 7.2 - 4:2:0 Subsampling support. The compression ratio is doubled. (Marcel) CVSTag: STEP7_2 (EDK/ISE8.1)
1) 4:2:0 Subsampling is supported and the compression efficiency is doubled.
2) Reduce file system resource usage. For xilfatfs, CONFIG_BUFCACHE_SIZE 2560 (default 10240), CONFIG_MAXFILES 2 (default 5), CONFIG_WRITE true (default false)
6. 2006/11/04 Step 1.2 - Add external memory support (Sunwei) CVSTag: STEP1_2c
The BMP file buffer is set to external memory and limitation is as large as 256MB if you use 256MB memory module. Code and data except for BMP file buffer is still in on-chip memory.