Intel’s Roadmap Targets Through-silicon Via Issues in Foveros Technology

July 29, 2021 by Jake Hertz

Knowing the issues with Foveros technology, Intel includes improvements, from interference to power consumption, into its roadmap. How is Intel aiming to improve this technology?

Earlier this week, Intel announced its new roadmap for the next five years and beyond, coming out with a wealth of information and talking points, from hopeful technologies to a possible transition to the angstrom era. The previous article discussed the overall goals laid out in the roadmap and the new nomenclature Intel will use to replace the "nm" to describe its technologies. 


Intel packaging improvements were laid out in their roadmap.

Intel packaging improvements were laid out in their roadmap. Screenshot used courtesy of Intel


This article will look more specifically at how the company plans to achieve those outlined goals and dive deeper into the proposed packaging technologies. 


A Background on Foveros 

One main aspect included in Intel's roadmap is improvements to its Foveros technology. To understand the advances that Intel is laying out, it's necessary first to understand Foveros, a die-to-die stacking technology that the company introduced back in 2019. 

The main idea behind Foveros technology consists of stacking multiple pieces of silicon on top of each other instead of side-by-side. This "3D" chip technology utilizes through-silicon vias (TSVs) to interconnect multiple IP blocks on different stacked pieces of silicon. This technology also uses "microbump" bonded connections, where pieces of copper covered in solder are bonded to create connections.

The benefits of this approach include higher logic density/decreased area and decreased parasitics due to shorter data path lengths. These benefits result in less power consumption, lower latency, and overall better signal integrity. 


Foveros is a face-to-face 3D IC technology.

Foveros is a face-to-face 3D IC technology. Image from WikiChip


However, this approach can have some drawbacks. First off, the exceptionally high density of a 3D IC means that the power density is also increased. All else equal, fitting more logic into a smaller area means higher power consumed per area, hence hotter temperatures. 

Another major concern with the Foveros 3D stacking is interference caused by routing power signals through TSVs. High currents from layer to layer through TSVs result in high interference levels, decreasing signal integrity and compromising performance. 

Finally, it's worth noting that microbump bonded connections generally don't scale well.

Now that the basics of Foveros have been covered let's take a look at Intel's future plans for the technology. 


Foveros Omni and Foveros Direct 

As part of its plan moving forward, Intel cited two new developments to Foveros technology: Foveros Omni and Foveros Direct.


Foveros Omni minimizes TSV penalties.

Foveros Omni minimizes TSV penalties. Screenshot used courtesy of Intel


Foveros Omni is Intel's new term for its omnidirectional interconnect, a packaging technology that seeks to solve the interference caused by power signals traveling through TSVs. 

The technology essentially allows for the top die to overhang from the base die, allowing for copper pillars to be built from the substrate up - connecting to the edges of the top die. This method allows for power to be provided to the top die without causing significant interference as before, which also has the further benefit of enabling the die-to-die bump pitches to scale down. 

Further, Intel states that Omni will have a bump pitch of 25 microns which is a significant increase over previous Foveros technology. 


Foveros Direct leverages copper-to-copper bonding.

Foveros Direct leverages copper-to-copper bonding. Screenshot used courtesy of Intel


Foveros Direct is another variation on Foveros technology, this one leveraging techniques in hybrid bonding. Instead of using microbump bonded connections, Fovero Direct utilizes direct copper-to-copper bonding. 

One benefit of this approach is that it further removes parasitics from the bump-to-bump connection, decreasing power consumption and latency. Beyond this, the technology further allows Intel to scale down its die-to-die bump pitch connections. Intel anticipates achieving a sub 10 µm pitch with Foveros Direct, further improving than Foveros technology. 


Looking and Moving Forward 

Though Foveros has only been around since 2019, Intel seemed to be aware of the setbacks and created plans to circumvent them with this newest roadmap. According to Intel, Foveros Omni and Foveros Direct are expected to be ready for volume manufacturing in 2023. 

The next article in this mini-series will cover RibbonFET and PowerVia, two new Intel technologies that they say will further help it achieve its lofty roadmap-defined goals.