Developing Voice-Activated Systems: A Low-Power Stereo ADC from Texas Instruments
This article will look at some of the most important features of TLV320ADC3100 which is TI’s newly-released ADC for voice-activated systems.
This article will look at some of the most important features of TLV320ADC3100 which is TI’s newly-released ADC for voice-activated systems.
TLV320ADC3100 is a stereo audio ADC which incorporates programmable sample rates, programmable gain amplifiers (PGA), integrated automatic gain control (AGC) mechanisms, digital filters, and a phase-locked loop (PLL). You could use the TLV320ADC3100 for applications such as smart speakers, voice-enabled assistants, and noise-cancellation systems.
The functional block diagram of the device is shown below.
Functional block diagram of the TLV320ADC3100. Image courtesy of TI.
Analog Inputs
The TLV320ADC3100 has four audio inputs which can be configured as differential or single-ended. The analog inputs of the device can be connected to a microphone or line analog input.
PGA and AGC
The selected analog inputs are applied to the PGA, which stands for “programmable gain amplifier.” The PGA provides a gain in the range of 0 dB to 40 dB, in steps of 0.5 dB. This allows the system to compensate for variations in the volume of the input sound. The IC includes a “soft-stepping” feature that prevents PGA changes from producing audible artifacts.
The automatic gain control (AGC) subsystem controls the PGA gain. The AGC algorithm of TLV320ADC3100 has several programmable parameters that can be used to customize the system for a given application. “Attack time” and “decay time” are two of these parameters.
Image courtesy of TI.
The attack time specifies the time it takes the AGC to bring a large output signal back to the nominal amplitude. By adjusting the attack time, we can prevent the system from responding too quickly to a large signal amplitude. Similarly, decay time determines the time to reach the target signal level when we have an output signal level smaller than the nominal value.
Delta-Sigma Modulator
The TLV320ADC3100 uses a delta-sigma modulator with 128-times oversampling in single-rate mode. The ADC supports sampling rates from 8 kHz to 48 kHz in single-rate mode, and up to 96 kHz in dual-rate mode. The oversampling A/D conversion along with the digital filtering relaxes the requirements for the analog anti-aliasing filter and allows the TLV320ADC3100 to use an integrated analog second-order filter with 20 dB attenuation at 1 MHz.
In a mono recording application, it’s possible to save some power by deactivating one of the ADC channels.
Digital Filters
As mentioned above, the TLV320ADC3100 employs oversampled A/D conversion. To obtain Nyquist rate data with high dynamic range, we need to further process the oversampled data. This digital signal processing can be easily obtained using the built-in digital filters of the TLV320ADC3100. For example, we can program the device to process the output of the delta-sigma modulator using the following block diagram.
Image courtesy of TI.
This is only one of the available options. For example, we can replace the 25-tap FIR filter with five biquad sections:
Image courtesy of TI.
We can choose the required processing blocks and adjust their programmable parameters based on the desired frequency response, group delay, and sampling rate.
Digital Audio Data Serial Interface
The data interface provides several flexible formats such as left- or right-justified data options, $$I^2S$$, and a time-division multiplexing (TDM) mode. The TDM mode can be helpful when a multichannel operation is required. The figure below shows an example timing diagram for the device.
Image courtesy of TI.
WCLK (i.e., word clock) defines the beginning of a frame. The word clock frequency is the same as the ADC sampling frequency. The bit clock, BCLK, controls the bit-by-bit data transfer across the serial bus. The data from the left channel is output after the rising edge of WCLK, and the data from the right channel is transferred after the falling edge. Note that the image above corresponds to the right-justified format of the TLV320ADC3100. That’s why the least significant bit (LSb) of the left channel immediately precedes the falling edge of WCLK (and the LSb of the right channel immediately precedes the rising edge of WCLK).
Keep in mind that this image is just one example of how to use the serial interface, which is quite flexible and thus can be customized according to the needs of the application.
For more information about the TLV320ADC3100, please refer to the device datasheet. You can find an example of the design procedure at the end of the datasheet.
If you have any experience with the TLV320ADC3100 or similar parts such as the TLV320ADC3001 or the TLV320ADC3101, please let us know in the comments below. What applications do you have in mind?
