A System-on-package Future? UCIe Consortium Aims for Open Chiplet Ecosystem

In the past decade, the largest trend in computing has been a shift towards the SoC architecture. However, the industry is now looking even further, with SoP being hailed as the next magic-bullet technology to push the industry forward into the next several decades.

 

A high-level graph showing a trend in packaging technology evolution. Image used courtesy of Rao R. Tummala

 

Bolstering this idea, Intel announced this week that it had joined forces with other major semiconductor giants to launch the UCIe Consortium.

This article will talk about the challenges of SoCs, the rise of the SoP, the UCIe Consortium, and what Intel hopes to achieve through this initiative.

 

SoC Design Challenges: Size 

While SoC has become the dominant technology in the industry today, many of its shortcomings are becoming increasingly apparent.

 

An example block diagram for an SoC. Image used courtesy of onsemi

 

One large challenge in SoC production today is that, as SoC die size increases to integrate more components and achieve higher performance, designs are starting to reach the die reticle limit, running up against the die reticle limit. 

This limit means that manufacturing is becoming increasingly infeasible, as we are reaching the maximum chip area that can be exposed to a single photomask during manufacturing. 

Increasing die size equals lower yields, which means less cost-efficient manufacturing and a slower time to market.

Another challenge is that interconnect parasitics become highly significant as these SoCs become physically larger, but the technology nodes become smaller. 

All in all, the increased wiring resistance and inductance lead to higher loss, more significant delay, and ultimately higher latency for the SoC. 

In the end, the global wiring delay in SOC becomes too high for computing applications. 

 

System-on-package Tackles System-on-chip Challenges

With these limitations in mind, many argue that to maintain progress moving forward, we must shift to the SoP.

The concept of an SoP is to take SoCs one step further. Instead of integrating multiple components into a single chip, the SoP combines multiple systems, also called chiplets, into a single package. 

As Rao Tummala explains, “...the SoP is akin to Moore’s Law for the IC.”

 

An example of an SoP can be thought of as integrating multiple ICs onto a single package. Image used courtesy of Rao R. Tummala

 

Overall, the SoP addresses many of the engineering challenges SoCs face today.

From a manufacturing perspective, SoPs having multiple smaller dies connected in a single package instead of a single, large die results in significantly increased yields. 

This benefit also eliminates the fears of running into the die reticle limit and affords us more room to grow and scale.

Additionally, SoPs can also help avoid parasitic-related latency, as global interconnects can be moved from the nanoscale level to the microscale level. This attribute leads to interconnects with larger widths, areas, and thicknesses, which means less detrimental interconnect parasitics.

Finally, integration on the chiplet level can easily enable a designer to optimize their design tradeoffs for a given market segment. 

A system designer can simply choose the necessary integrated systems, such as compute, memory, and I/O, based on the end application needs without the need for different die designs.

 

Intel and the UCIe Consortium 

Recognizing the needs of the industry, and the promise of the SoP, Intel, along with other major players such as Arm, TSMC, and Samsung, have launched the UCIe Consortium.

The consortium was founded to address a glaring challenge in SoP design: what standards will be used to interconnect chiplets within an SoP?

 

Overview of the UCIe Consortium's initial goals. Image used courtesy of the UCIe Consortium

 

To address this, the UCIe Consortium was formed as an open specification that seeks to define this interconnection to enable an open chiplet ecosystem and ubiquitous interconnect at the package level.

It is stated that the initial focus of the Consortium will consist of:

• The Physical Layer: addressing and developing die-to-die I/O standards
• The Protocol Layer: developing CXL/PCIe technology for near-term volume attach
• Building out a well-defined specification that will ensure interoperability and evolution within the SoP industry

From Intel’s perspective, joining the consortium will help to ensure Intel’s technology is a foundational aspect of SoPs moving forward. 

Specifically, the consortium plans to build on Intel’s Advanced Interface Bus (AIB), meaning future SoPs and chiplets will be easily integrated with Intel technologies.

With this potential industry shift and consortium, it will be interesting to see how these new standards could develop within the industry.

 

Featured image used courtesy of Intel

 

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What do you think about this consortium or consortiums in general? Do you think that the SoP is the future? Let us know your thoughts in the comments down below.