STMicroelectronics Brings UVLO (Under-voltage Lockout) to SiC FETs

March 26, 2021 by Jake Hertz

When designing a circuit, especially in high voltage applications, safety is a major concern. A new isolated gate driver is bringing under-voltage safety features to SiC FETs.

When deciding which components to use, a thorough understanding of their biasing conditions is critical, not only for the design to function properly, but also to prevent any safety concerns.

One main consideration designers may come across is whether to use silicon-carbide (SiC) or silicon (Si). While SiC can be thought of in the same way as Si in many instances, there are fundamental differences in their operation. Specifically, the I-V curve for a SiC FET trends differently than that of a-Si FET, which leaves room for improper operation and potential safety hazards if not biased correctly.


Circuit block performance varies from intended as the input voltage varies.

Circuit block performance varies from intended as the input voltage varies. Image used courtesy of Texas Instruments


However, in real applications, biasing can never be exact. This imperfection is caused by fluctuations in the power supply or battery voltages varying because of current draw or parasitics. Specific measures can ensure the safe operation of SiC FETs in dynamic and unpredictable use cases. 

To better understand those fundamental differences between SiC and Si, it is necessary to look at their operating regions.


SiC vs Si Operating Regions 

Both SiC and Si MOSFETs behave similarly, however, their exact operating behavior is not identical when it comes to their respective I-V curves

In a Si MOSFET, the ID (drain current) vs. VDS (drain-source voltage) curves initially stay close to one another and then begin to separate and saturate at different levels depending on the VGS (gate-source voltage). In theory, imagine that the gate voltage is too low in the proposed devices.

In this case, the device saturates at lower current levels, leading to extremely high conduction losses from the device not being fully turned on but experiencing high VDS values.


I-V curves for SiC (left) and Si (right).

I-V curves for SiC (left) and Si (right). Image used courtesy of Texas Instruments


In a SiC MOSFET, the same trends are observed; however, the difference is that the operating region has a larger dependence on the gate voltage. As seen in the figure above, SiC FETs tend to saturate at much lower currents depending on the gate voltage. This saturation rate makes the device more susceptible to high conduction losses than the Si FET. 

As seen in the previous examples, gate drivers can play a large role in SiC designs and benefit from adding functions to keep the voltage in check. 


UVLO (Under-voltage Lockout) for SiCs 

SiC FETs, which are often used in high power applications, need high gate drive voltages and cannot afford fluctuations, lest they undergo significant conduction losses and thermal dissipation.

One solution is called under-voltage lockout (UVLO). UVLO is a function integrated into ICs to disable a circuit block if specific voltages (i.e., supply, gate drive) are too low. If the input voltage is below a predefined threshold, the UVLO circuit will not pass the value or disable a circuit block entirely. 

In a UVLO example, the input voltage is taken, and a resistive divider network is used to compare the voltage to a reference.


A UVLO circuit.

Example UVLO circuit block. Image used courtesy of CTC


When the voltage on R3 is higher than the reference, the comparator outputs low, keeping the switch off and keeping the EN signal high. When that voltage is lower than the reference, the switch is turned on, driving EN low and effectively turning off the following circuit block.

In this way, UVLO prevents circuit operation at undesired voltage levels and creates a safer circuit. 

UVLO is a simple safety precaution that can be equipped with various IC designs.


STMicroelectronics’ New Gate Driver 

This UVLO circuitry is the focal point of STMicroelectronics' newest isolated gate driver IC.

Designed specifically for safe control of SiC FETs, the STGAP2SiCS operates up to 1200V and can produce gate drive voltages up to 26V. For improved safety, the IC has increased its UVLO threshold from previous generations, now up to 15.5V, thus not allowing SiCs to be driven by any value lower. 


Block diagram of the STGAP2SiCS

Block diagram of the STGAP2SiCS. Image used courtesy of STMicroelectronics


Meant for industrial applications, this IC can produce up to 4A of gate drive, making its maximum power delivery up to 104W from one IC. Further safety comes from its offering of 6kV of galvanic isolation between input and gate driver.

Additional safety features include low power standby modes, hardware interlocks (to prevent cross conduction), and thermal shutdown protections. 



With SiCs and other wide-bandgap semiconductors becoming increasingly popular, engineers need to continually develop ways to ensure their operation is efficient and safe. STMicroelectronics is doing just that with their newest gate driver IC for SiCs, introducing UVLO and other safety features all on one chip.