My previous article introduced dynamic random access memory, or DRAM. DRAM is a type of RAM that needs to be dynamically refreshed every so often. This is because DRAM uses an array of capacitors to store digital information. When a charge is present, a binary '1' is stored, while the absence of a charge indicates a binary '0'. DRAM is organized into a number of banks which are further divided into rows and columns. The capacitors are found at the intersection of these rows and columns.
Figure 1 shows a x4 DRAM bank introduced in the previous article.
Figure 1. Memory array with sense amplifiers and decoders
But how does one actually use DRAM? How does a processor or memory controller tell the DRAM to return or store specific data in a specific location? Understanding the commands sent to a DRAM chip is the first step in actually designing a system that uses DRAM.
Fundamental DRAM Commands
While DRAM can differ greatly from one manufacturer to the next, there are a set of fundamental commands that the majority of DRAM chips use to perform actions. To execute a command, a memory controller will write values to a set of inputs within the DRAM. These inputs belong to the DRAM's command decoder. This decoder has a 4-bit input where, depending on the combination of bits, a different command gets requested.
Figure 2. DRAM decoder with inputs (the # symbol indicates that these are active-low signals)
These active-low inputs all have names and are typically defined as CS, CAS, RAS, and WE:
- CS: chip select (enables or disables the command decoder)
- RAS: row address strobe
- CAS: column address strobe
- WE: write enable
These four inputs allow for up to 16 commands to be built into the DRAM.
Figure 3 shows a simplified view of a DRAM chip. It can be used as a reference to better understand the different commands listed.
Figure 3. DRAM reference. Image used courtesy of Alliance Memory
The command inhibit, or sometimes called device deselect, disables the ability to execute commands on the DRAM. To use the command, the CS input is brought high (and other inputs are disregarded, i.e., “don't care”). As mentioned earlier, CS stands for chip select and disables the command decoder. Thus, it makes sense that this would get pulled high for inhibiting commands.
Activate is essentially the row access command. Meaning, it opens up a row and moves the charge from the capacitors into the sense amplifiers. Accessing a row is always done before a column in DRAM. This command is paired with inputs to a bank address register (that selects the current bank) and a row address register (that selects the desired row). One important note on the activate command is that whichever row is currently open remains open until a precharge command is issued (more on precharge later). To use this command most DRAMs require CS and RAS to be pulled low, while CAS and WE are pulled high.
Precharge deactivates the row currently open in a bank. When issued a precharge command, the DRAM is told to restore the values read from the row of capacitors. This is done by the sense amplifiers and when completed prepares the bank for another row access. Precharge is performed by pulling CS, RAS, and WE low and leaving CAS high.
The read command can also be thought of as a column read command. When combined with a proper bank address and column address, the data recently moved into the sense amplifiers from an activate command (row access) is now pushed onto the data bus. DRAMs often include a “Read and Auto-Precharge” command that performs the column read and then closes/precharges the row. This way, a separate precharge command need not be issued. If the same row, but a different column, needed to be accessed then a precharge would not be issued at all and the row would be left open. To use the read command CS and CAS are pulled low, while RAS and WE are pulled high.
A write command is virtually the same as a read, except for the direction of the data. During a write command, data is pulled off of the data bus and put into the selected bank, row, and column. Auto-precharging can be performed much like a read and closes the currently activated row when the write is done. To perform a write, CS, CAS, and WE are pulled low, while RAS is held high.
Figure 4 shows an activate command (row access) in yellow, with a subsequent read/write command (column access) in blue. The data at the intersection of the row and column, shown in green, is moved between the sense amplifiers and data buffers.
Figure 4. Highlighting the activate and read/write commands
What differentiates DRAM from other kinds of random access memory is the fact that the capacitors used for memory storage will leak charge over time. Thus, DRAM is dynamic because it needs to be periodically refreshed. This is where the refresh command comes in. In DRAM, the refresh command is issued every so often. One important aspect of refreshing is that any active banks should be precharged before the command is issued. To perform a refresh CS, RAS, and CAS are pulled low with WE high.
After refreshing, the DRAM keeps track of the last refreshed row and increments a refresh counter so that the next refresh command will operate on the next row. Keep in mind that when a refresh command is issued, the current row in every bank is refreshed. Most DRAMs will perform 8192 refresh cycles every 64 ms. That's every 7.813 μs. This has remained constant despite growing device densities.
Other common DRAM commands include NOP (No Operation), Burst Terminate, and Load Mode Register. NOP is used to force the DRAM to do nothing. This is useful when the DRAM needs to wait, for instance if it is currently being refreshed. In reality, read and writes to DRAM are done in short bursts. Burst terminate will truncate the read or write command, i.e., stop it prior to finishing. DRAM can be placed into different modes. These modes are changed via the Load Mode Register command.
Figure 5 shows a truth table listing the decoder input combinations for executing different DRAM commands.
Figure 5. DRAM commands — Truth Table
This article discussed the different commands that a DRAM is capable of performing. These commands are initiated by a memory controller or CPU that is interacting with the DRAM.
Commands are executed by writing to the inputs of the DRAM command decoder. Any system that needs to do serious work will have onboard memory. If you understand these commands, implementing DRAM in your next project will be a whole lot easier.