Of all the serial interfaces used for embedded devices, I2C stands out as my personal favorite. While it may not have the same throughput as other serial communication methods, the ability to control so many devices with only two lines, while having multiple masters, makes I2C an awesome tool for the embedded engineer trying to manage cost, pin count, and complexity.
Sometimes, though, design constraints can complicate an I2C implementation. The I2C buffer is one tool that can make things a little bit easier.
- Introduction to the I2C Bus
- The I2C Bus: Hardware Implementation Details
- The I2C Bus: Firmware Implementation Details
- I2C Design Mathematics: Capacitance and Resistance
Considering I2C Bus Capacitance
With the 7-bit addressing scheme, a theoretical 128 devices can be connected to an I2C bus. Some of these addresses are reserved, leaving only 112 available. With the new 10-bit addressing scheme, even more devices can be connected. However, every device added to the bus increases the overall bus capacitance, which can be surprisingly high when all the PCB capacitance and device capacitances are added up. In order to comply with the standard, once the 400 pF maximum is reached, no more devices can be placed on the bus. One way of getting around this is to add an I2C buffer to your design. The picture below, taken from this application note (PDF) published by Texas Instruments, shows a typical I2C bus with associated bus capacitance.
Figure 1. Typical I2C bus with associated bus capacitance. Diagram courtesy of TI (PDF).
Introducing the I2C Buffer
When operating in Standard or Fast mode, the I2C bus has a maximum bus capacitance of 400 pF. In Fast Mode Plus, this is increased to 500 pF. Once that limit is reached, any more capacitance puts you outside the standard and outside device specifications. This problem can be especially troublesome when devices and pull-up resistors are chosen and specified before the engineer realizes that more devices need to be added.
The I2C buffer divides the I2C bus into two separate buses, while still allowing devices to communicate across it. This effectively cuts your total bus capacitance wherever the buffer is placed, because the separate buses have separate bus capacitances. This means that for the same pull-up resistors, we get a lower RC time constant and thus a shorter rise time. This ability to reduce rise time is one of the main reasons buffers are used.
Figure 2. Buffer inserted into an I2C bus, cutting bus capacitance in half. Diagram taken from this app note (PDF).
Static Voltage Offset (SVO)
The bidirectional nature of I2C communication means that I2C buffers must employ special techniques to avoid “locking up” the bus. As you can see in the diagram below, if the master pulls the line low, then the slave side gets pulled low. However, the logic low on the slave side also pulls the master's side low. Consequently, when the master tries to release the bus, the slave side is still driving low.
Figure 3. Buffers can lock up the bus if not designed correctly
One solution to this problem is to use a static voltage offset (SVO). Essentially, a low-voltage Zener diode is used to create an additional threshold voltage on one side of the buffer, such that a logic-low on the SVO side of the buffer can be either a “below the SVO” logic low or an “above the SVO” logic low, depending on whether the logic low was driven by the master side or the slave side. Thus, a controller inside the buffer can determine the origin of the logic low and use this information to prevent lock-up.
Multiple buffers can be used along the bus as a means of managing capacitance. You can’t assume that SVO voltage levels will be identical, even when using the same exact part, and thus multiple buffers must be configured so as to make sure that two SVO voltages are not connected together. The SVO also has to be checked against the input voltage of the slave device, to ensure that it is well below the 30% threshold. Many devices use an SVO of 0.5 V, but the value can range at least from 0.1 V to 0.6 V.
Examples of I2C Buffers
The PC9515A from Texas Instruments is described as a dual bidirectional I2C buffer. It can be used to run a 5 V bus alongside a 3.3 V bus, so it functions as a logic-level translator as well. Here's an application example from the datasheet:
Figure 4. PC9515A running with two different bus voltages
The LTC4311 from Linear Tech/Analog Devices is a different type of I2C buffer. Actually, the part is described not as a buffer but as an “accelerator.” It is connected in parallel with the other devices on the bus, and its internal circuitry compensates for large amounts of bus capacitance by detecting positive signal transitions and then injecting additional current that causes the transition to occur more rapidly. The following diagram shows how the LTC4311 is used.
Figure 5. Diagram of how the LTC4311 is used. Taken from the LTC4311 datasheet (PDF).
I2C Buffers in Industrial Applications
In the industrial automation world, electronic systems are often controlling highly sensitive processes that can't be allowed to fail. Mission critical applications require both the hardware and software to work no matter what. This had led to huge investments in redundant systems and controllers.
Another application of I2C buffers is creating a redundant bus. Two buffers, both running back to the same master, can be used to provide a failsafe in case one bus locks up or is compromised. A redundant I2C bus with redundant devices can be used to mitigate the risk of bus or device failure. Below is an example of what this type of system might look like.
Figure 6. An example of an I2C bus system with redundant devices.
Essentially, the master can use the EN pin to control which bus is currently being communicated on and switch to the inactive bus in case of a failure. The secondary bus could be periodically checked to make sure it's still ready to take over if the primary fails. Setups like this add robustness to a design and can be a huge benefit when reliability is a prime concern.
This redundant-bus configuration creates two independent groups of slave devices. As a result, it can also be useful when one master needs to communicate with slaves that operate in different modes (e.g., some of the slaves use Fast Mode and the others are in Standard Mode).
This article introduced the I2C buffer and its applications. It can be used to reduce bus capacitance, control rise times, add additional devices to the bus, interface devices operating at different voltages, or even to implement a redundant bus. Understanding how a buffer works and when to use it provides another tool for the design engineer's toolbox.
Great designs are a mixture of experience, creativity, and a mastery of the fundamentals. I hope that your understanding of I2C is now a little bit better and that the design challenges that come with it seem a little less daunting.