# Learn Analog Circuits: Types and Applications of Current Mirrors

## The current mirror is an important analog building block that finds application in such diverse areas as DC biasing and current-mode signal processing.

Learn more about analog design in this introduction to the current mirror, including how this circuit is implemented in analog ICs.

The current mirror is an important analog building block that finds application in such diverse areas as DC biasing and current-mode signal processing. This block comes in various incarnations, which we will investigate below:

- Basic mirror
- Mirror with beta helper
- Widlar current source
- Wilson mirror

We'll begin by looking at some basic characteristics of a bipolar junction transistor (BJT).

### Background: BJT Characteristics

To set the background, consider Figure *1*, which shows the* i _{C}-v_{CE}* characteristics of an

*NPN*BJT for different base-emitter voltage drives

*V*.

_{BE}

*(a) (b)*

**Figure 1**. Using PSpice to display the i_{C}-v_{CE} characteristics of an NPN BJT. For v_{CE} < 0.2 V the BJT is in saturation (Sat), whereas for v_{CE} ≥ 0.2 V it is operating in the forward-active (FA) region.

**Figure 1**. Using PSpice to display the i

_{C}-v

_{CE}characteristics of an NPN BJT. For v

_{CE}< 0.2 V the BJT is in saturation (Sat), whereas for v

_{CE}≥ 0.2 V it is operating in the forward-active (FA) region.

We observe that, for *v _{CE}* ≥ 0.2 V, all curves are essentially flat, indicating the BJT’s ability to sink current independently of the collector voltage (so long as this voltage is prevented from dropping below about 0.2 V). Even though

*V*is incremented in equal 10 mV steps,

_{BE}*i*increases in geometric fashion. In fact, in the forward-active (FA) region,

_{C}*i*is related to

_{C}*v*exponentially as

_{BE}

*Equation 1*

*Equation 1*

where *I _{s}* is a scaling factor called the

*saturation current*, and

*V*is another scaling factor called the

_{T}*thermal voltage*because it is proportional to absolute temperature

*T*. For a low-power BJT,

*I*is typically in the femtoampere range (1 fA = 10

_{s}^{–15}A).

Moreover, *V _{T}* = 26 mV at room temperature. Figure

*2a*shows the PSpice plot of Equation (1) for a BJT with

*I*= 2 fA (this value has been chosen so that with

_{s}*v*= 700 mV the BJT gives exactly

_{BE}*i*= 1.0 mA).

_{C}

*(a) (b)*

**Figure 2.** Using PSpice to *plot** (a) i*_{C} vs. v_{BE} and (b) v_{BE} vs. i_{C}.

**Figure 2.**Using PSpice to

_{C}vs. v

_{BE}and (b) v

_{BE}vs. i

_{C}.

The inverse of Equation (1) is

*Equation 2*

*Equation 2*

To plot *v _{BE}* as a function of

*i*via PSpice, we connect the base and collector terminals together to operate the BJT in what is called the

_{C}*diode mode*, and then we apply a test current

*i*, as shown in Figure

_{T}*2b.*

### Basic Current Mirror

The basic mirror, shown in Figure *3a*, consists of a pair of *matched* BJTs fabricated (or mounted) in close proximity to each other so that their characteristics (*I _{s}* and

*V*)

_{T}*track*each other with temperature and time.

*(a) (b)*

**Figure 3**. (a) Basic current mirror, and (b) its i_{O} vs. v_{O} characteristic for i_{I }= 1 mA and V_{CC} = 10 V.

**Figure 3**. (a) Basic current mirror, and (b) its i

_{O}vs. v

_{O}characteristic for i

_{I }= 1 mA and V

_{CC}= 10 V.

Assuming negligible base currents, we note that diode-connected *Q _{1}* responds to the input current

*i*by developing a voltage drop

_{I}*v*according to Equation (2) shown above.

_{BE}Since *Q _{2}* is experiencing the

*same*

*v*as

_{BE}*Q*, we must have

_{1}*i*=

_{C2}*i*, by Equation (1), so

_{C1}*Q*

_{2}*mirrors*

*Q*. Assuming negligible base currents, we thus have

_{1}*i*=

_{O}*i*

_{I}.Compared to Figure *1b*, the expanded view of Figure *3b* indicates that the curve in the FA region exhibits a nonzero slope. This stems from the so-called *Early Effect* ^{[1]}, as a consequence of which the projections of all curves meet at a common point on the negative axis called the *Early Voltage* *V _{A}*, as shown in Figure 4.

*Figure 4. **Expanded** view of Figure 1b, illustrating the consequences of the Early Effect.*

*Figure 4.*

The slope of an *i _{C}* curve in the FA region is denoted as

*1/r*, the reciprocal of resistance. Applying simple geometric reasoning to Figure 4, we have the slope (=

_{o}*1/r*) ≈

_{o}*I*, or

_{C }/ V_{A}

*Equation 3*

*Equation 3*

where *I _{C}* represents the current at the left edge of the FA region.

The PSpice example shown uses *V*_{A }= 60 V, so for *I _{C}* = 1 mA we have

*r*≈ 60/10

_{o}^{–3}= 60 kΩ. This means that the Norton equivalent seen by the load is a 1 mA current sink with a parallel resistance of 60 kΩ. For every volt increase in

*v*,

_{O}*r*is responsible for an increase in

_{o}*i*of (1 V)/(60 kΩ) = 16.7 µA.

_{O}

### Current Mirror with Beta Helper

We now wish to take a closer look at the base currents of the basic mirror of Figure *3a*. It is well known that a BJT’s base current *i _{B}* is related to the collector current

*i*as

_{C}*i*=

_{B}*i*

_{C }/

*ß*, where

*ß*is the BJT’s

*current gain*. Typically,

*ß*≈ 100, though integrated-circuit BJTs may have

*ß*≈ 250. With reference to Figure

*3a*, KCL at

*Q*’s collector node implies

_{1}*i*=

_{I}*i*+

_{C1}*i*+

_{B1}*i*≈

_{B2}*i*+

_{C1}*2i*=

_{B1}*i*+

_{C1}*2i*/

_{C1}*ß*=

*i*(1 + 2/

_{C1}*ß*), or

*Equation 4*

*Equation 4*

indicating that *i _{C1}* (and hence

*i*, by mirror action) will be a bit

_{C2}*less*than

*i*. For instance, with

_{I}*ß*= 100,

*i*and thus also

_{C1}*i*(=

_{O}*i*=

_{C2}*i*) will be about 98% of

_{C1}*i*. Should this error be intolerable, we can enlist the help of a third BJT

_{I}*Q*to supply

_{3}*i*and

_{B1}*i*in the manner of Figure

_{B2}*5a*.

*(a) (b)*

**Figure 5.** (a) Current mirror with *beta** helper, and (b) Widlar current source. *

**Figure 5.**(a) Current mirror with

This reduces the error current at *Q _{1}*’s collector node by a factor of about

*ß*, so Equation (4) still holds, but with

*ß*replaced by

*ß*

^{2}.

### Widlar Current Source

In DC biasing applications it is often necessary to synthesize a current *i _{O}* <<

*i*. The circuit of Figure

_{I}*5b*, named for its inventor Bob Widlar, achieves this goal by means of a resistor

*R*in

*series*with

*Q*to reduce

_{2}*Q*’s base-emitter voltage drop as

_{2}

*Equation 5*

*Equation 5*

In this connection, it helps to remember the following *rules of thumb* so dear to practicing engineers:

- To raise (lower)
*i*by an_{C}*octave*, you need to raise (lower)*v*by 18 mV (because e_{BE}^{±18/26}≈ 2^{±1}). - To raise (lower)
*i*by a_{C}*decade*, you need to raise (lower)*v*_{BE }by 60 mV (because e^{±60/26}≈ 10^{±1}).

As an example, suppose we have *i _{I}* = 1 mA (= 1,000 µA) and we want

*i*= 20 µA. We can think of 20 as the result of dividing 1,000 by 10 to get 100, dividing 100 by 10 to get 10, and then multiplying 10 by 2 to get 20. So,

_{O}*R*must drop (60 + 60 –18) mV = 102 mV. Then, R = (102 mV)/(20 µA) = 5.1 kΩ.

### Wilson Current Mirror

There are applications in which it is desirable that a current mirror (*a*) be exempt from the beta-error of Equation (4), and (*b*) exhibit a much higher output resistance than the *r _{o}* of Equation (3), so that it can closely approximate an

*ideal current source*or

*sink*. The mirror of Figure

*6a*, named for its inventor G. R. Wilson, achieves both objectives with just one additional transistor

*Q*(two birds with one stone). This elegant circuit can be analyzed systematically

_{3}^{[1]}, but here we shall limit ourselves to an intuitive discussion.

*(a) (b)*

**Figure 6.** (a) Wilson current mirror, and (b) its i_{O} vs. v_{O} characteristic for i_{I} = 1 mA and V_{CC} = 10 V.

**Figure 6.**(a) Wilson current mirror, and (b) its i

_{O}vs. v

_{O}characteristic for i

_{I}= 1 mA and V

_{CC}= 10 V.

We note that *Q _{3}* carries the same current as

*Q*because they are in series, and

_{2}*Q*, in turn, mirrors the current of

_{1}*Q*, so, the left and right halves of the circuit carry

_{2}*identical*currents. This is corroborated by the fact the

*Q*draws its base current from the left half, whereas

_{3}*Q*draws its base current from the right half, in a give-and-take fashion. (A systematic analysis

_{1}^{[1]}predicts an error of the type of the beta helper.)

Now, if we attempt to raise *v** _{O}* by, say, 1 V, the Early Effect would cause

*i*to increase by (1 V)/

_{C3}*r*. This would cause an increase in

_{o}*v*, by Equation (2), and this, in turn, would cause an increase in

_{BE2}*i*, by Equation (1). Having become a bit more conductive,

_{C1}*Q*would be letting less base current into

_{1}*Q*, forcing the latter to conduct a bit less. In words, any attempt to raise

_{3}*i*is met by a reaction that tends to nullify such an attempt. In fact, this is negative feedback! (A systematic analysis

_{C3}^{[1]}predicts a Norton resistance of about

*ßr*/2.) The flatness of the

_{o}*i*curve of Figure

_{O}*6b*confirms the excellent characteristic of the Wilson mirror!

### Current Mirrors at Work

It can be fun to look at integrated-circuit schematics and identify the presence and purpose of current mirrors (CMs). For instance, turning to the 741 op-amp of Figure 7, we identify the following CMs:

- The trio
*Q*is a basic CM with beta helper. This CM forms an_{5 }- Q_{6 }- Q_{7}*active load*for the differential input stage made up of the left half (*Q*-_{1 }*Q*) and right half (_{3}*Q*-_{2 }*Q*). Ideally, the two halves should be perfectly matched, but in practice there may be some mismatch, resulting in an input offset voltage_{4}*V*. The emitters of_{OS}*Q*and_{5}*Q*are equipped with 1 kΩ resistors to allow for the creation of an externally induced imbalance equal but opposite to the imbalance of the left and right halves, so as to null_{6}*V*. (For the procedure to null the offset voltage_{OS}*V*, please refer to the fifth figure of this page in the AAC textbook.)_{OS} - The pair
*Q*-_{10 }*Q*is a Widlar current sink. The bias current for diode-connected_{11}*Q*is established by_{11}*R*, which is actually a dual-purpose component because it also biases diode-connected_{5}*Q*._{12} - The basic CM
*Q*-_{12}*Q*is designed to source_{13}*two*currents independently, one to provide an*active load*function for common-emitter amplifier*Q*, and the other to_{17}*bias*the circuitry of the output stage. The current entering*Q*’s emitter is steered separately by_{13}*Q*’s two collectors, in percentages determined by the collector areas._{13} - The pair
*Q*_{8 }-*Q*forms yet another basic CM, which, in connection with the Widlar sink_{9}*Q*_{10 }-*Q*, is designed to provide the DC bias current for the two halves of the input stage._{11} - Can you identify other CMs? Yes indeed, it’s the pair
*Q*-_{23}*Q*. Under normal operating conditions, these BJTs are off because_{24}*Q*is off. However, should an overload condition arise at the output,_{21}*Q*will go on, turning on also_{21}*Q*. By mirror action,_{24}*Q*will go on and starve_{23}*Q*of base current to limit the power dissipated by the output stage._{16}

**Figure 7**. *Circuit** schematic of the 741 **op-amp** (courtesy of Fairchild Semiconductor Corporation).*

**Figure 7**.

Next, let us look at the CFA of Figure 8.

**Figure 8**. Circuit schematic of a *current-fee**dback* amplifier (CFA).

**Figure 8**. Circuit schematic of a

*dback*amplifier (CFA).

This circuit uses a pair of Wilson CMs, *Q*_{5 }- *Q _{6}* -

*Q*and

_{7}*Q*-

_{8}*Q*-

_{9}*Q*, to replicate, respectively, the collector currents of

_{10}*Q*and

_{1}*Q*and provide their difference at the common base terminals of

_{2}*Q*and

_{13}*Q*. In a way, the upper CM acts as an

_{14}*active load*for the lower CM, just as the lower CM acts as an active load for the upper CM. Furthermore, the DC biasing circuitry consists of the current sources

*I*and

_{3}*I*, and the current sinks

_{13}*I*and

_{4}*I*, which are shown in symbolic form for simplicity. But, if we were to look at a more detailed schematic, we would find that also these sources and sinks are implemented in CM form.

_{14}

### Conclusion

This article briefly reviewed BJT operation, then it explored four types of BJT current mirrors: the basic mirror, the mirror with beta helper, the Widlar current source, and the Wilson mirror. In the final section, we saw some examples of how current mirrors are incorporated into analog integrated circuits.

Current mirrors can also be implemented using CMOS technology. AAC’s article entitled The Basic MOSFET Constant-Current Source is a good place to start if you want to learn about the CMOS version of the current mirror.

#### References

[1] http://online.sfsu.edu/sfranco/BookAnalog/AnalogJacket.pdf

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