Typical 3.3 V or 5 V logic signals are generally adequate for short-distance chip-to-chip (i.e., intraboard) communication, even with clock frequencies in the megahertz range. A well-designed PCB can be considered a fairly protected environment, where digital signals are not likely to experience severe degradation due to noise or parasitic reactance.
But the situation changes when digital data, especially high-speed data, leaves this protected environment—e.g., when it must travel to a separate portion of the system through long cables or intense EMI. Even intraboard communication can become problematic when strong noise sources are present or when very high data rates (e.g., in the hundreds of megabits per second) are required.
From One Wire to Two Wires
The general remedy in such cases is to move from single-ended logic to differential signaling. RS-422/485 is an excellent interface, but it is not optimized for high speed. Other options include current-mode logic (CML) and low-voltage positive emitter-coupled logic (LVPECL). But, in my experience, a more common choice is low-voltage differential signaling (LVDS).
LVDS is a standardized interface for high-speed, point-to-point digital communication. “Point-to-point” means one transmitter and one receiver; LVDS is not intended for facilitating communication between numerous devices in a system, but rather for rapidly and efficiently moving large amounts of data from one device to another.
LVDS uses (you guessed it!) low-voltage-swing, differential signals, as follows:
The nominal common-mode voltage is 1.2 V, and the nominal voltage range for each signal in the differential pair is 150 mV above to 150 mV below the common-mode voltage. This means that each signal’s voltage is changing by only 300 mV—about an order of magnitude lower than the voltage swing of a single-ended 3.3 V logic signal.
Despite the small voltage difference between logic low and logic high, the benefits of differential signaling (in conjunction with twisted wires and shielded cables) allow LVDS to provide highly reliable communication.
Far from being merely a data-integrity concern, low-voltage-swing signaling saves power and increases speed:
- Less voltage across the termination resistors reduces current, and lower supply voltages in general reduce power consumption (remember, CMOS power dissipation is proportional to VDD squared).
- Voltage transitions cannot occur instantaneously; it takes time for a signal to move from one voltage to another, so less distance between logic low and logic high enables higher-frequency operation by reducing the time required for each logic transition.
Not Out of Reach
LVDS is a high-performance standard that can achieve data rates approaching, or maybe even exceeding, 1 gigabit per second (though speed must be reduced as cable length increases). But don’t be intimidated—an abundance of user-friendly integrated circuits makes LVDS a very approachable interface. It is not difficult to translate from standard logic to LVDS and back to standard logic using readily available LVDS drivers and receivers, and termination is straightforward:
LVDS can be particularly valuable when the device providing the to-be-translated signals (such as a microcontroller) is too slow to generate serial data at the desired frequency. In such cases you can use an LVDS serializer in conjunction with an LVDS deserializer—the former converts parallel standard-logic inputs to serial LVDS outputs, and the latter converts the serial LVDS data back into parallel standard-logic signals (this datasheet for a serializer/deserializer pair gives you an example of what I’m referring to).
LVDS offers high speed and low power, as well as convenient IC-based implementation. It’s a great alternative to single-ended logic when you need robust, high-bandwidth, point-to-point data transfer.