Multiply-Accumulate Operation (MAC)

Details
Category: Arithmetic Core
Created: November 21, 2018
Updated: November 19, 2019
Language: VHDL
Other project properties
Development Status: Alpha
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
In computing, especially digital signal processing, the multiply–accumulate operation is a common step that computes the product of two numbers and adds that product to an accumulator. The hardware unit that performs the operation is known as a multiplier–accumulator (MAC, or MAC unit); the operation itself is also often called a MAC or a MAC operation.
Reference: https://en.wikipedia.org/wikiMultiply-accumulate_operation