USB 2.0 Device Core with UTMI Interface

USB 2.0 Device Core with UTMI Interface


Category: Communication Controller

Created: March 26, 2014

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Alpha

Additional info: Design done, FPGA proven

WishBone compliant: Yes

WishBone version: n/a

License: LGPL


USB Peripheral Interface


This component is a simple USB Peripheral Interface (Device) implementation with an AXI4-Lite slave register interface, and with a UTMI interface for connection to a USB PHY.

It has been designed to support USB2.0, but currently has been only tested in Full Speed peripheral mode (12Mbit/s).


  • USB 2.0 Device mode support.
  • Simple register data read/write interface (low performance / not DMA based).
  • UTMI PHY interface (see my UTMI to ULPI Conversion wrapper project to allow connection to a ULPI PHY e.g. USB3300)
  • Current build configuration has 4 endpoints


  • Only tested for USB-FS (Full Speed / 12Mbit/s) only.
  • AXI4-L address and data must arrive in the same cycle.


Provided with a USB-CDC test stack (USB Serial port) with loopback/echo example.

To make this functional on your platform;

  • Set USB_DEV_BASE to the correct address for the peripheral.
  • Implement the millisecond timer functions in timer.h.
  • Change USB_BYTE_SWAP16 in usbf_defs.h if your CPU is big endian.


Verified under simulation then tested on FPGA as a USB-CDC mode peripheral (USB serial port) against Linux & Windows PCs.