Ethernet 10GE Low Latency MAC

Ethernet 10GE Low Latency MAC


Category: Communication Controller

Created: November 15, 2012

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Stable

WishBone compliant: No

WishBone version: n/a

License: LGPL


This is a fork of the xge_mac and was released by the Computer Architecture Group ( of the University of Heidelberg.

Main changes in this fork:
-Unwanted FIFOs removed
-Latency reduced due to the removal of the FIFOs and a new CRC implementation
-Interface very similar to the one of the Xilinx MAC

This core is in production use.