SRL Feature FIFO in Xilinx FPGAs

SRL Feature FIFO in Xilinx FPGAs


Category: Memory Core

Created: January 02, 2008

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Stable

Additional info: Design done

WishBone compliant: No

WishBone version: n/a

License: LGPL


Synchronous FIFO's based upon the SRL feature found in Xilinx FPGA's.

Built to be small.

In a Spartan 3, the 8 bit wide , 16 bit deep FIFO utilises
19 Luts
of which 8 are used as SRL, 11 as Logic.


Pure VHDL, no instantiated components, all inferred
small size