The Intel 4004 was the first commercially-available single-chip CPU. Developed by Intel in 1969 for the Busicom company for use in the Busicom 141-PF calculator, and made commercially available for other uses in November 1971, the 4004 CPU and the other MCS-4 family chips were used in embedded applications into the mid-1980s.
This project is a translation of the pMOS, dynamic-logic MCS-4 chip set design into static-logic, functional Verilog that can be synthesized for most any FPGA. The implementation intentionally uses the net naming convention found in the 400x simulator available from the 35th Anniversary website (http://www.4004.com). Plans include support for the 4004 CPU, the 4001 ROM, 4002 RAM, and 4003 Output expander chips.
Components from this project can be used to synthesize a complete, working, cycle-accurate, MCS-4 system in an FPGA.
A somewhat rambling blog describing this project, and companion project to implement the 4004 CPU using discrete components, can be found here: http://insanity4004.blogspot.com
Intel has licensed the use of the 4004 CPU schematics, chip mask images, and other documentation under a non-commercial license: http://www.intel.com/museum4004ipnclicense.htm
Intel also provided written confirmation to use other MCS-4 related materials in this work and publish non-commercially the recreated source materials of 4001 ROM, 4002 RAM and 4003 schematics and 4001 layout under a Creative Commons license. It is available now 'By-attribution, Non-Commercial, Share-Alike' (BY-NC-SA) as described here: http://creativecommons.org/licenses/by-nc-sa/3.0legalcode
Since this project is derived from the schematics and other documentation licensed above, it necessarily carries the same non-commercial license grants and restrictions.
Nov 12, 2012:
At long last, some Verilog source code! I've uploaded the core modules that make up the 4004 CPU. Test bench code and modules that make up the 4001 ROM will be uploaded in the near future.
Sep 24, 2012:
Although I've listed the project as being in the "planning" state, the 4004 CPU is fully coded and runs simple test programs in simulation. The ROM portion of the 4001 is mostly coded and sufficiently functional to support the 4004 CPU testing; the I/O portion is partly coded and totally untested.
Verilog source code will be posted after I've done some clean-up to align it more closely with the OpenCores HDL modeling guidelines and include appropriate license info in the file comments.