32-bit interface CoreConnect PLBv46 to Wishbone Bridge

32-bit interface CoreConnect PLBv46 to Wishbone Bridge

Details

Category: System on Chip

Created: July 25, 2008

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Beta

Additional info: FPGA proven

WishBone compliant: Yes

WishBone version: n/a

License: n/a

Description

PLBv46 to Wishbone Bridge

This is a simple CoreConnect PLBv46 to Wishbone bridge that can allow Wishbone peripherals to be used on Xilinx processor designs. It conforms to the sub-set of the PLBv46 specification adopted by Xilinx in the EDK.

Features

- PLBv46 Slave Attachment (non bursting)
- 32-bit interface to PLBv46 bus.
- 32-bit interface to Wishbone bus.

- Supports
- Handling of Retries.
- User can set the retry wait time.
- User can set number of times to retry
- Result of unsuccessful retry is a PLBv46 bus error ack.
- Handling of Bus Errors
- User can set how long to wait for a bus-time out (no WB ack)
- Results in a PLBv46 Bus Error

Status

- New