Dallas One-wire Protocol with a DS1821 Top Level Demo

Dallas One-wire Protocol with a DS1821 Top Level Demo

Details

Category: Uncategorized

Created: April 23, 2004

Updated: January 27, 2020

Other project properties

Development Status: Stable

WishBone compliant: No

WishBone version: n/a

License: n/a

Description

Dallas one-wire protocol with a DS1821 top level demo

This project was done for a senior project in the ASIC senior project sequence at Oregon Institute of Technology in Klamath Falls, Oregon under the instruction of Ralph A. Carestia.

I wrote this code real quick for my Senior Project and found the whole thing of having to reset between commands unintuitive. (I had to call Maxim to figure that out) but once I got that far I was disco.

This project was tested on an Altera UP2 board. The design requires a 1uS period input clock and the clk_divider.vhd file divides the clock down from the 25.175 or clk to the needed 1uS period.

DS1821_2.vhd is the top level design. It was version 2 and there for it has the _2. Some compilers may not like that the entity is DS1821 and the file name has the _2 on it but thats an easy fix.

The actual core is housed in the one_wire.vhd file. Essentially when you reset it it does an init pulse to the chip and once the chip answers and we're ready to go you get a ready pulse out. When you get that ready pulse you simply put a value on the write data vector and then pulse the write line. You are expected to send the write line low again before the next ready signal or it will be seen as a subsequent write. Its fine for you to de-activate the write line as soon as you see ready go low. Once you see a ready line you can pulse the read line in the same fashion and the core will send 0xFFh to the device and sample the line at the appropiate times. When the read is done the 8 bit value in the read buffer is what you got.

The seg_decode.vhd is just as you would think a 7-seg decoder that allows you to see the value in the register after you read it. The DS1821 top level is coded in such a way that it can be included into yet a higher level and thus the need for the temp valid signals and such.

Features

- Communicates with the Dallas 1-wire devices
- Can easily be setup to run at faster speeds just by changing input clocks
- Can give the re-init sequence at anytime simply by resetting the core
- The core resyncs with the device on a reset
- Top level gives a good example of how to send commands in hex to the chip
- Talks directly to the DS1821 on the UP2 board with no modifications
- Top level was coded in such a manner that you can just reset it and wait for the temp valid bit to be set before grabbing the 8 bit value.

Status

- Tested working in FPGA although the code is ugly and beta. After I get some time and my senior project is completed I'll clean it up and add more comments and what not.
- Would like to add temperature conversion later but not sure what is all entailed in getting that math to go for me. If anyone wants to help add that that would be cool!