Why SoCs Need NoCs: Network on Chip and the Future of Computing
In a complex heterogeneous computing ecosystem, the development of network-on-chip interconnects is essential to the progress of system-on-chip technology.
The computing ecosystem has fully embraced the concept of heterogeneous computing—the result being the proliferation of the system-on-chips (SoCs). SoCs can now be found in virtually every high-performance computing platform on the market.
A less frequently discussed but equally important piece of technology is the network-on-chip (NoC). As SoCs continue their upward trajectory, NoC development will only continue to increase as well. Recently, UK-based Sondrel underscored the importance of the NoC, announcing that it uses Arteris' FlexNoC IP as the NoC backbone of Sondrel SoCs.
An example NoC is highlighted in blue (left) and situated on a floorplan (right). Image used courtesy of Sondrel
In this article, we’ll discuss the challenges of heterogeneous computing, the need for the NoC, and some details of Arteris' FlexNoC.
SoCs and the Challenges of Heterogeneous Computing
An SoC is a single-chip solution that consists of several different computing and functional blocks within the same piece of silicon. SoCs embrace the concept of heterogeneous computing and hardware acceleration, where specialized computing blocks are used for specific, compute-intensive workloads. For this reason, it is common to see an SoC consisting of some more general-purpose computing blocks, like CPUs and GPUs, as well as many accelerator blocks, such as neural processing units (NPUs) and digital signal processors (DSPs).
While this scheme leads to higher performance and power efficiency, it has several control and management issues. In data-intensive applications, SoCs are faced with the challenge of how to control, organize, and manage the large amounts of data they are expected to work with. From both a floor-planning perspective and a systems perspective, controlling data flow to and from memory and the number of disparate functional blocks presents a non-trivial obstacle.
What is an NoC?
To address these data-related issues, almost every SoC relies on a network-on-chip (NoC).
An NoC interconnects almost every part of an SoC, creating a clear and well-defined path for data to flow from block to block. Typically, an NoC will consist of multiple segments of wires and routers laid out to reduce parasitics that lead to greater loss and delay across the SoC. This normally takes the form of a city-like grid structure.
An NoC in a mesh topology. Image used courtesy of ACM Digital Library
The NoC controls the flow of data throughout the SoC through the use of network interface (NI) modules. These modules are often used to transform data packets generated by the processor cores into fixed-length, flow-control digits. These digits allow the routers within the NoC to appropriately direct data to the desired functional block.
Traditionally, NoC functions can be defined into one of several layers, including application, transport, network, data link, and physical layers. For this reason, an NoC router will require both hardware and software implementations such that it can support the functions of the given layers.
Sondrel Uses FlexNoC
On June 22, 2022, Sondrel revealed that it uses Arteris' FlexNoC IP as the NoC backbone for all of its SoC solutions.
Arteris explains that an NoC interconnect makes up the SoC architecture. Image used courtesy of Arteris
Sondrel specifically praises FlexNoC’s ability to reduce wire count within its NoCs. Arteris claims to achieve this feat by leveraging transport layer packetization and serialization capabilities. The company does this in such a way that it better understands which parts of the NoC require less wire area and optimizes accordingly. Beyond this, Sondrel lauds FlexNoC's ability to reduce power consumption through various power management features such as clock gating.
Like Sondrel, many companies around the industry are competing to produce the best NoC IP to give rise to SoCs with reduced area and power consumption while also making SoC design easier and more accessible.