32-bit Signed Integer Divider
Details
Category: Arithmetic Core
Created: March 06, 2013
Updated: January 27, 2020
Language: Verilog
Other project properties
Development Status: Alpha
Additional info: Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
A divider that calculates the quotient and remainder of a division operation in multiple clock cycles. The dividend, divisor, quotient and remainder are all 32-bit signed integers. By taking the advantage of a shifter that can shift more than one bit (up to 9 bits) during each cycle of computation, it takes less cycles to finish than a radix-2 nonrestoring divider.