Marvell Builds Out First 3nm SerDes and Parallel Interconnects

April 26, 2023 by Jake Hertz

With an eye on today's heavy data infrastructure, Marvell has implemented its SerDes and parallel interconnect technology on TSMC’s 3nm process.

While the semiconductor industry has traditionally focused on transistors, the interconnect is now garnering attention as well. There are numerous factors that contribute to this interest, including increased clock frequencies, smaller node sizes, and new technologies such as chiplets. 

Last week, Marvell Technology announced that it had successfully demonstrated its advanced semiconductor interconnect technologies on a 3nm node for the first time. In this article, we’ll look at the growing importance of interconnects and Marvell’s latest announcement of its SerDes and parallel interconnect technology on TSMC's 3nm process.


Eye diagrams of Marvell’s 3nm SerDes

Eye diagrams of Marvell’s 3nm SerDes. Image courtesy of Marvell Technology


Interconnects for Modern Chips

In today’s semiconductor industry, the interconnect has become a major bottleneck in chip design.

One major reason is the increasing prominence of interconnect parasitics in a modern chip. Decreasing transistor node sizes results in device-to-device interconnects having much smaller geometries and greater resistances. By the same token, chips are becoming much more densely integrated, meaning parasitics from inductive and capacitive coupling is becoming a much more prominent concern for designers. Other factors like increasing clock frequencies also contribute.


As process technologies scale down, the interconnect delay far exceeds the transistor gate delay

As process technologies scale down, the interconnect delay far exceeds the transistor gate delay. Image courtesy of Bohr et al.


The result of increased interconnect parasitics is that the interconnect delay has become a larger bottleneck than the transistor delay, meaning that the interconnect is the largest bottleneck for chip speed. In the same way, interconnect parasitics have become a major contributor to overall chip power consumption. 

The severity of this issue is further exacerbated by the proliferation of chiplets for the next wave in computing, where systems are composed of multiple chiplets connected by high-speed interconnects. For the semiconductor industry to continue to grow and provide greater performance generation after generation, developers must innovate current interconnect designs.


Marvell Scales Down SerDes and Parallel Interconnects

Marvell recently released a series of SerDes and parallel interconnect solutions for advanced semiconductor interconnects. Back in 2020, Marvell released the industry’s first 112 G 5nm SerDes for data centers, which was part of the company’s efforts to develop high-performance, chip-to-chip interconnects for future computing infrastructure.

Last week, the company continued these R&D efforts with the announcement of its interconnect technology demonstrated on a 3nm node. Specifically, the company claims that it implemented its 122 G XSR SerDes, Long Reach SerDes, PICe Gen 6 SerDes, and a 240 Tbps parallel die-to-die interconnect on TSMC’s 3nm node.

According to Marvell, the move to a 3nm node will help the company unlock lower power and higher performance interconnects for applications like chiplets, custom ASICs, Ethernet physical layer devices, and more.