When I first got started in electronics a little over two decades ago, most of the parts were designed for plated-through-hole (PTH) mounting, and it was unusual to find a part that had pins with less than 0.1” spacing. Now it’s uncommon to find parts that use PTH mounting and have pins spaced that far apart.
Things have gotten small and we are on the path for things to get much, much smaller. If you do not already own a trinocular microscope, you might consider investing in one along with a pair of delicate tweezers.
Here's a look at two companies that have recognized that small is big business.
Microconnex manufactures multi-layer flexible PCBs with trace/space width of as low as 0.75 mil. That allows over 650 traces per linear inch. That is a significant difference from what appears on typical PCBs. An 8 mil trace/space allows 63 traces per linear inch, and a 5 mil trace/space would allow up to 100 traces per inch.
Microconnex 4-layer PCB from Microconnex.com
When I visited Microconnex at Sensors Expo last week, as I was looking at these PCBs before me, I was thoroughly impressed. I had to examine them with a microscope to make out any sort of detail.
When I spoke to one of the Microconnex associates about the current state of technology, he said that, with as advanced as they are, the PCB manufacturers are still several generations behind the IC manufacturers. I couldn’t imagine how this might be possible—until I met Invensas.
Invensas, part of Xperi, has developed the technology required to vertically assemble silicon wafers. Moore’s Law has famously been approaching its asymptotic limit these last several years at the 10 nm fabrication node (see our articles over the years on breakthroughs that keep Moore's Law relevant, like the Department of Energy's Lawrence Berkeley National Laboratory's 1nm transistor or IBM, GlobalFoundries, and Samsung's 5nm chip).
So if you can’t easily cram more transistors onto a 2D silicon wafer, why not start packing them vertically to fit more silicon wafers in a package?
Wire-bond tip micrograph from Invensas BVA PoP technology whitepaper from Invensas.
Many companies can place a single wafer beneath a single MEMS sensor. Invensas can vertically bond many wafers and/or dies in multilayer stacks. Their proprietary Digital Bond Interconnect allows for 250,000 interconnects per mm². For reference, a competing technology that uses micro-pillar bumps allows only 500-1000 interconnects per mm². This is a difference of several orders of magnitude and it has important implications for thermal and electrical impedance.
Image sensors can have pixels that sit directly atop the image processor and simultaneously capture each pixel. This will instantly capture a full-frame image with no rolling shutter effect. Microprocessors can be affixed directly atop their memories instead of next to them, shrinking the package size, eliminating traces, and decreasing EMI. Parallel interfaces can be run vertically or horizontally inside of a single package.
I’ve never designed at the wafer-level, but I imagine that this technology simultaneously fills wafer-level engineers with both glee and dread, as their jobs just became exponentially more complicated as design moves into the 3-dimensional space.
Overcoming the Limitations Placed on Circuit Size
Up until now, the size of a component has been dictated by manufacturing and material science limitations. But we have seen manufacturers and material scientists make steady and predictable progress overcoming those limitations. Circuits and components will continue to shrink until we press up against the boundaries imposed by the laws of physics. When that time comes, countless engineers will lay awake nights pondering those laws and looking for loopholes that allow them to continue to cram functionality into smaller and smaller spaces.