COVID-19 Puts Spotlight on Open-Source RISC-V Cores, IP

May 20, 2020 by Antonio Anzaldua Jr.

Remote work during this pandemic has shed light anew on the virtues of RISC-V, which has just gotten more accessible.

The COVID-19 pandemic has given RISC-V new opportunities to prove they can help engineers develop chips without worrying about funding. Recently, several corporations have begun providing RISC-V core processors that will allow programmers to build complex designs without paying for proprietary hardware licenses. The stated intention for many of these corporations is to broaden designers' resources, allowing them to contribute to diagnostic, preventative, and treatment innovations.

In this article, we'll briefly touch on the strengths of RISC-V—especially at a time when many engineers feel cut off from the full breadth of design resources—and explore how several organizations are making this tool more readily available.


The RISC-V Architecture

RISC (reduced instruction set computing) designs make hardware designers’ lives easier in terms of power efficiency, reliability, and remote support—but it comes with a lofty price tag. Developers are not granted access to RISC designs without meeting required proprietary hardware licenses to companies such as Intel, Arm, and Micron. 

RISC-V, on the other hand, is an embedded core processor with an open standard instruction set architecture (ISA) under free, non-restrictive licenses. According to RISC-V International, RISC-V brings a new wave of design tools, boot builders, programming languages, stability testing, and simulation designs for any full custom chip development. Programmers can design a custom core and download a free standard core evaluation development kit, which includes Verilog RTL and FPGA bitstreams. 


RISC-V Foundation Ratifies Process Trace Specifications

The RISC-V Foundation is a non-profit corporation controlled by its dedicated members. They have a simple goal: drive the adoption and implementation of a free and open RISC-V ISA to developers worldwide.


RISC-V Foundation Members

The RISC-V Foundation comprises more than 500 members building the first open, collaborative community of software and hardware innovators. Image used courtesy of RISC-V Foundation


Early this month, the foundation announced the ratification of a processor trace specification. This specification will provide a new standard trace encoder algorithm. The algorithm will allow hardware engineers to preview instructions while the core processor is executing throughout the design process. 

This trace specification is especially helpful to designers as they debug since it exposes accurate, detailed traces of activity while isolating significant trace portions. The RISC-V Foundation has more than 200 members, including Samsung, Google, Nvidia, Western Digital, NXP, Micron, Qualcomm, and Raspberry Pi. 


SiFive Pledges Open Access to Their IP During Pandemic

Along with a new processor trace specification, another RISC-V development comes from SiFive, which has pledged to open access to its intellectual property (IP), so designers can help fight COVID-19. 

SiFive, established in 2015, plans to democratize access to custom silicon, improving quality and reducing time to market. During these unprecedented times, SiFive has provided access to its E21 Standard Core embedded processor. Their hope is that designers will use this processor in MCU applications for in-demand healthcare devices, like ventilators.  SiFive says its RISC-V Core IP is the most silicon-deployed RISC‑V solutions in the world.


E76 block diagram

Block diagram of one of SiFive's "E" Core IPs for 32-bit embedded cores—the E76. Image used courtesy of SiFive

The software associated with the SiFive E21 Standard Core processor will offer an online chip-design tool that allows users to build customizable products with various design options.

By offering this processor at no cost, SiFive may enable designers to build control systems for life-saving equipment. Their pledge also gives hope for scientists, engineers, and developers to accelerate the development of diagnostics, vaccines, therapeutics, medical equipment, and software solutions to combat the urgent health crisis.  


CHIPS Alliance Rolls Out Hardware at No Cost

Like SiFive and the RISC-V Foundation, the Common Hardware for Interfaces, Processors, and Systems (CHIPS) Alliance is also providing aid during the pandemic. 

The CHIPS Alliance is bringing its newly-enhanced SweRV Core EL2 and EH2—developed by Western Digital—to the hardware community with hopes of accelerating RISC-V innovation in healthcare products, artificial intelligence (AI), internet of things (IoT), mobile devices, and other embedded applications.


Diagram of SweRV Core EH2 and EL2

Diagram of SweRV Core EH2 and EL2. Image used courtesy of Western Digital


This announcement coincides with RISC-V International partnering with GlobalPlatform to simplify security design for IoT devices and processors.

The CHIPS Alliance is an organization that develops and hosts open-source hardware code, interconnect internet protocols (IP), and design tools. The CHIPS Alliance aims to provide a barrier-free collaborative environment to lower the cost of developing IP and tools for hardware design.

SweRV Core EH2 is an embedded RISC-V processor designed for embedded devices supporting data-intensive edge, AI, and IoT applications. The EL2 also utilizes the RISC-V core but is ultra-small and optimized for applications such as state-machines sequencers and waveform generators.

The CHIPS Alliance will be hosting an online event through Zoom to discuss both the SweRV Core EH2 and EL2. At the event, CHIPS will introduce its mission of supplying software support and solutions for programmers free of cost. 


RISC and Reward

In review, some of the overarching benefits of RISC designs include:

  • Power efficiency
  • Simple, clean-slate design
  • Modular instruction set architecture (ISA)
  • System stability 
  • Variable length instruction encoding
  • Easily integrate with FPGA programmable logic chip
  • Built-in queue management

Since programmers can write in an accessible array of 32 registers, RISC-V allows data to be immediately operated on while providing information housekeeping. Designers will not need to seek external memory for a large number of CPU tasks, reducing overall energy consumption. Built-in queue management is where most modern processor architectures get their speed—a great feature for decoding internal instruction queues. 

Organizations and companies across the industry are pushing for free RISC-V events and resources. RISC-V may change the way the developers work together and collaborate—creating an open hardware and software ecosystem for designers to make an impact on COVID-19.


Learn More About RISC-V