# How to Buffer an Op-Amp Output for Higher Current, Part 4

March 23, 2016 by Robert Keim## If you choose to buffer with MOSFETs instead of BJTs, you need to consider the relationship between gate capacitance and instability.

If you choose to buffer with MOSFETs instead of BJTs, you need to consider the relationship between gate capacitance and instability.

### Supporting Information

- Introduction to Operational Amplifiers
- Insulated-Gate Field-Effect Transistors (MOSFET)
- Negative Feedback, Part 5: Gain Margin and Phase Margin

### Previous Articles in This Series

- How to Buffer an Op-Amp Output for Higher Current, Part 1
- How to Buffer an Op-Amp Output for Higher Current, Part 2
- How to Buffer an Op-Amp Output for Higher Current, Part 3

### The Stability Question

In the previous article we saw that it is possible to use MOSFETs instead of BJTs in standard op-amp current-buffering circuits. One significant advantage of MOSFET implementations is the negligible steady-state current required from the op-amp’s output stage—the MOSFET’s drain current is controlled primarily by the gate-to-source voltage, not the current flowing into the gate, and furthermore only small (in our context, insignificant) leakage currents can flow into the gate because it is insulated from the rest of the FET. Thus, you can generate very large load currents with even a very puny op-amp. However, the MOSFET’s insulated gate is a benefit and a liability. That insulated gate means capacitance, and you will end up with a seriously troublesome circuit if you have too much capacitance connected to the op-amp’s output.

Actually, it’s a little more complicated than that. As you may know, op-amps have a limited ability to safely drive capacitive loads. The issue is stability—the op-amp’s output resistance combines with the load capacitance to form a pole that introduces an additional 90° of phase shift into the loop-gain transfer function. This additional phase shift can lead to excessive ringing or even oscillation. (My Negative Feedback Series, particularly Part 4 through Part 10, contains an abundance of information on stability; load-capacitance-induced instability is discussed in Part 9.) You can look in the op-amp’s datasheet to get an idea of how much load capacitance that particular device can safely drive; however, this information is not directly applicable to our current-buffering circuit because the MOSFET’s gate capacitance is not connected between the op-amp’s output terminal and ground. Part of the capacitance (namely, the gate-source capacitance) is connected to ground through the load resistance, and we will see that this series resistance influences the stability of the circuit.

### Charge or Capacitance?

You may have noticed that MOSFET datasheets report the “gate charge” more prominently than input capacitance. This is also the case with LTspice, which displays only three parameters when you open the window to select a new NMOS or PMOS device; one of these parameters is gate charge, and there is no mention of capacitance. Manufacturers focus on gate charge because it is a better spec for calculating and comparing switching speeds:

\[time\ required\ to\ turn\ on\ MOSFET=\frac{gate\ charge}{charging\ current}\]

For the sake of convenience, I’ll refer to gate charge when I need to convey a device’s input capacitance in relation to that of another MOSFET. For our purposes, it is sufficient to understand that more gate charge corresponds to more load capacitance. We really don’t have much need for the actual capacitance value because we won’t attempt to analytically predict phase margin or overshoot percentage. Actually, that brings me to my next point. Full disclosure: The complexity of this circuit—the MOSFET’s current–voltage characteristics, the various parasitic capacitances, the op-amp’s output resistance, the effect of different amounts of load resistance—exceeds my ability to precisely understand and explain what’s going on in the context of stability. What I can say with confidence is that a large gate capacitance can make the circuit less stable, so be careful. It is also safe to say that, in general, lower load resistance leads to more instability. Beyond that, I recommend that you simulate, and hope that the simulations are at least somewhat consistent with reality.

### Baseline

We’ll explore this topic by looking at some illustrative step-response plots. For more information on using step response to assess stability, see Negative Feedback, Part 10: Stability in the Time Domain. You can also perform frequency-domain stability simulations by “breaking the loop”; this is discussed in Negative Feedback, Part 9.

Let’s start with a baseline step response—i.e., what the step response looks like without any buffering transistor or load capacitance. Here is the circuit:

The load resistor was chosen based on the typical maximum output current of the LT6203, namely, 45 mA; the input is a 500 mV step, and (500 mV)/(45 mA) = 11.1 Ω. Here is the plot:

The delay from input to output reflects the op-amp’s slew-rate limitation, and the moderate overshoot is consistent with the fact that the LT6203 has plenty of phase margin at unity gain.

### Overshoot, Ringing, Oscillation

Now let’s insert an FDC2512 NMOS (gate charge = 8 nC) and see what happens.

The overshoot amplitude has increased, and we can discern a slight oscillatory tendency. However, this step response is nothing to be concerned about. The next plot shows the effect of reducing the load resistance from 12 Ω to 2 Ω.

We observe some additional oscillatory behavior with the lower load resistance, but the amplitude of the overshoot (about 60 mV, or 12%) indicates that the circuit is still sufficiently stable (12% overshoot corresponds to phase margin of about 57°).

Now let’s change the FET to a part with more gate capacitance. This plot includes results for the FDS5680, which has a gate charge of 30 nC, compared to 8 nC with the FDC2512. The load resistance for both FET circuits is 2 Ω.

Obviously, we have a problem here. Our overshoot percentage has increased to about 60%, which means that the phase margin is around 15°—not even close to the 45° needed for sufficient stability. Just so we can appreciate the oscillatory vigor produced by a generous dose of load capacitance, here are results for the FDB8030L (gate charge = 120 nC):

### BJTs Have Capacitance Too

The foregoing demonstration does not mean that FETs are universally worse than BJTs in the context of load-capacitance-induced instability. I admit that I don’t favor MOSFETs when it comes to buffering op-amp output current, and not just because there’s something pleasantly old-fashioned about BJTs. The fact is, I don’t like worrying about stability any more than I have to, and consequently I prefer to avoid the MOSFET’s gate capacitance. However, the above results for the FDC2512 (gate charge = 8 nC) indicate that you can maintain adequate stability by choosing an appropriate part (especially considering that you can get high-current FETs with gate charge well below 8 nC). Furthermore, BJTs bring their own capacitive load in the form of *pn*-junction capacitance. Take a look at the following plot, which shows results for the FDC2512 FET and the 2SCR293P BJT (both with R_{LOAD} = 2 Ω).

We can see that the BJT’s effect on stability is by no means negligible; actually, the overshoot in the BJT trace is slightly worse than that in the FET trace.

### Conclusion

Both MOSFETs and BJTs contribute load capacitance that can degrade the stability of a negative-feedback op-amp circuit. But you need to be especially careful with MOSFET gate capacitance, which in general is higher than a BJT’s input capacitance and which varies significantly from part to part. I initially thought that adding some series resistance between the op-amp’s output terminal and the gate of the FET would mitigate stability problems, but my simulations indicated that this approach is not effective (actually, the series resistance made the oscillations worse). My recommendation is to seek out low-gate-charge parts and then use simulations to ensure that the op-amp/MOSFET combination maintains adequate stability.

5 CommentsAre these parts you are actually using in a design? MOSFETs with an input capacitance of over 1,300 pF? Or did you choose these parts just to have a good bad example? It certainly emphasizes the problem.

Valuable commentary , I was fascinated by the details - Does anyone know where my company might be able to acquire a sample CA WG-001 copy to type on ?

That’s wonderful article. Do you have idea about noise characteristics and drift/offset of such current-amplified design ?

Use case: Imagine you need high current high precision voltage source to feed an ADC reference input and it’s sensors in a ratio-metric design. The sensors and reference need about 20-40 mA .(JavaScript must be enabled to view this email address). You employ a zero-drift chopper-stabilized low noise op-amp to buffer your RC-filtered reference and a high-betha low noise transistor, say BC549C. Will you get the low noise zero-drift performance ?

I also thought that a small series resistance (10 ohm or 100 ohm) between the op-amp output and the NMOS gate would reduce overshoot, but my own simulation agrees with the statement above - this approach is not effective.