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Once upon a time, there was a company that brought out its own variation of the Berkeley Spice program. Called HSPICE, this program specialized in making refined models for MOS transistors. It made many variations of these models, which were known as “levels.”
Many companies bought their own levels, like boxes at the opera. AMD had three of them, and Siemens acquired two. Motorola, National Semiconductor, Sharp, Cypress, Siliconix, and a few others only got one. By 1995, there were 39 such levels, and we poor ordinary folks couldn't access most of them—they could only be used by the company that had sponsored them.
At last, good old Berkeley came to the rescue. A team of researchers developed BSIM (Berkeley Short-channel IGFET Model). The team stayed with it, through BSIM1, BSIM2, BSIM3, and even BSIM4. These models divided the MOS transistors in ever finer structures, tracking the trend toward geometries far below 1 µm.
As of this writing, BSIM3.3 is the dominant model in the industry, leaving the many HSPICE levels in the dust. Naturally, HSPICE took the BSIM models and made its own version, adding more levels.
The increasing BSIM refinements have a drawback: the number of parameters has become very large, so large that it would take an entire book to explain them. For digital ICs, which require the utmost switching speed, this simply has to be accepted. For analog designs, which invariably use larger dimensions to obtain adequate performance (especially for matching), it’s a burden only grudgingly tolerated. MOS model-making has become an art dominated by the digital realm, of limited use to the analog designer.
BSIM Model Parameters
In a modern BSIM model, you’re confronted by a mass of data that is almost always presented in an arbitrary way, lacking an organization which would make it more understandable. To help in a minor way, the model parameters are grouped in the table below. The bold-faced parameters are absolute values; all others are modifiers. Parameters in square brackets are temperature coefficients.
BSIM parameters for MOS transistors
| Threshold voltage: | VTHO, K1, [KT1, KT1L], K2, [KT2], K3, K3B, DVT0, DVT0W, DVT1, DVT1W, DVT2, DVT2W, VBM, VOFF, KETA, PSCBE1, PSCBE2 |
| Mobility: | UO, UA, [UA1], UB, [UB1], UC, [UC1] |
| Saturation: | VSAT, [AT], A0, AGS, A1, A2, B0, B1, DELTA, EM, PCLM, PDIBLC1, PDIBLC2, PDIBLCB, DROUT, PVAG, AGS, ALPHA0, BETA0 |
| Sub-threshold: | ETA0, ETAB, NFACTOR, DSUB |
| Geometry: | W0, DWB, DWG, LL, LLN, LW, LWL, LWN, WL, WLN, WW, WWL, WWN |
| Capacitances: | CGS0, CGD0, CGB0, CJ, MJ, MJSW, PBSW, CJSW, MJSW, CJSWG, MJSWG, PBSWG, PB, CGSL, CGDL, CKAPPA, CF, CLC, CLE, DLC, DWC, ELM, CDSC, CDSB, CDSCD, CIT |
| Resistances: | RSH, RDSW, [PRT], PRWB, PRWG, WR, LINT, WINT |
| Process Parameters: | TOX, XJ, XT, NCH (PCH), NGATE, NLX, NSUB, GAMMA1, GAMMA2, JS, [XTI], NJ, JSSW |
| Noise: | AF, KF, EF, EM, NOIA, NOIB, NOIC |
Binning for Different Transistor Geometries
BSIM models also allow binning: several models are written for different geometries of the same device and then selected to fit into a range of gate widths and lengths. The parameters LMIN and LMAX specify minimum and maximum length; the parameters WMIN and WMAX do the same for width.
This isn’t really necessary for the parameters listed in the above table, as some foundries, notably AMS, manage to create equally accurate models without binning. However, the Monte Carlo variations should be tied to channel area, which requires width and length. Note that the multiplier M is used for transistors with a channel width beyond WMAX.
For more detail on the many parameters, you’ll need to consult the Berkeley documentation. Be forewarned that these are lengthy documents.
