Using this circuit, you will also learn how to test a digital circuit and complete a logic truth table. Not only will you learn the basics of building and testing circuits for digital logic gates, but the completed circuit can easily be adapted to test multiple NAND gates or other logic gate functions. Any gate type may be tested with two switches, two pulldown resistors, and an LED to indicate output status.
Caution! The 4011 IC is a CMOS and, therefore, sensitive to static electricity!
Step 1: Review the datasheet for the 4011 chip when you build your circuit. Shown in Figure 2 is my own rendition of what a typical 4011 datasheet shows.
However, don’t just follow this illustration! It is important that you develop the skill of reading datasheets, especially pinout diagrams, when connecting IC terminals to other circuit elements. The datasheet’s connection diagram is an essential piece of information to have to insure you are making the right connections.
In the breadboard illustration, I’ve shown the circuit built using the lower-left NAND gate: pins #‘s 1 and 2 are the inputs, and pin #3 is the output. At first, using an 8-position switch and a 10-segment LED bar graph may seem excessive since only two switches, and one LED are needed to show the operation of a single NAND gate. However, the presence of those extra switches and LEDs makes it convenient to expand the circuit and helps make the circuit layout both clean and compact.
Digital logic circuitry does not use split power supplies as some op-amps do. Like op-amp circuits, though, the ground is still the implicit point of reference for all voltage measurements. If I were to speak of a high signal being present on a certain pin of the chip, I would mean that there was full voltage between that pin and the negative side of the power supply (ground).
Step 4: Connect all of the unused digital inputs to either VDD or ground. Note how in Figure 4, all the inputs of the unused gates inside the 4011 chip are connected either to VDD or ground. This is not a mistake but an act of intentional design. Since the 4011 is a CMOS IC, and CMOS circuit inputs left unconnected (floating) can assume any voltage level merely from intercepting a static electric charge from a nearby object. Leaving inputs floating means that those unused gates may receive any random combinations of high and low signals.
Why is this undesirable if we aren’t using those gates? Who cares what signals they receive if we are not doing anything with their outputs? The problem is if static voltage signals appear at the gate inputs that are not fully “high” or fully “low,” the gates’ internal transistors may begin to turn on in such a way as to draw excessive current. At worst, this could lead to damage to the chip. At best, it means excessive power consumption.
It matters little if we choose to connect these unused gate inputs high (VDD) or low (ground) so long as we connect them to one of those two places. In the breadboard illustration of Figure 4, I show all the top inputs connected to VDD, and all the bottom inputs (of the unused gates) connected to the ground. This was done merely because those power supply rail holes were closed and did not require long jumper wires.
Step 5: Next, make sure all of our unused outputs are left unconnected (floating). Please note that none of the unused gate outputs in Figure 4 have been connected to VDD or ground and for good reason since they have been left floating. If I were to connect them to one of the power supplies, I may be forcing a gate to assume the opposite output state that it’s trying to achieve, which is a complicated way of saying that I would have created a short circuit.
Imagine a gate that is supposed to output a high logic level (for a NAND gate, this would be true if any of its inputs were “low”). If such a gate were to have its output terminal directly connected to the ground, it could never reach a high state (being made electrically common to the ground through the jumper wire connection). Instead, its upper (P-channel) output transistor would be turned on in vain, sourcing maximum current to a nonexistent load. This would very likely damage the gate!
Gate output terminals, by their very nature, generate their own logic levels and never float in the same way that CMOS gate inputs do.
Step 6: Add pulldown resistors to the digital inputs. The two 10 kΩ resistors shown in Figures 3 and 4 are placed in the circuit to avoid floating input conditions on the NAND gate we are using. When a switch is closed, the respective input will be directly connected to VDD and therefore be “high” with a small current passed through the pulldown resistors. When a switch is open, the 10 kΩ pulldown resistor provides a resistive connection to the ground, ensuring a secure “low” state at the gate’s input terminal. This way, the input will not be susceptible to stray static voltages.
Step 7: With the NAND gate connected to the two switches at the inputs and one LED at the output, you are now ready to develop a truth table for the NAND gate. Even if you already know what a NAND gate truth table looks like, this is a good exercise in experimentation: discovering a circuit’s behavioral principles by induction. Create a 2-input truth table as shown in Table 1.
Table 1. A 2-input truth table.
The “A” and “B” columns represent the two input switches, respectively. When the switch is on, its state is “high” or 1. When the switch is off, its state is “low,” or 0, as ensured by its pulldown resistor. The gate’s output, of course, is represented by the LED, whether it is lit (1) or unlit (0). After placing the switches in every possible combination of states and recording the LED’s status, compare the resulting truth table with what a NAND gate’s truth table should be.
As you can imagine, this breadboard circuit is not limited to testing NAND gates. Any gate type may be tested with two switches, two pulldown resistors, and an LED to indicate output status. Just be sure to double-check the chip’s pinout diagram before substituting it pin-for-pin in place of the 4011. Not all quad-gate chips have the same pin assignments.
Step 8: An additional improvement you might want to make to this circuit is to assign a couple of LEDs to indicate input status in addition to the one LED assigned to indicate the output. This makes its operation a little more interesting to observe, It also has the further benefit of indicating if a switch fails to close (or open) by showing the true input signal to the gate rather than forcing you to infer input status from the switch position. The connections for the two input indicator LEDs have been added in the breadboard circuit illustration of Figure 5.
Learn more about the fundamentals behind this project in the resources below.
In Partnership with Würth Elektronik eiSos GmbH & Co. KG
by Jake Hertz