Analog-to-Digital Conversion

Tutorials abound on simple ADC strategies, so your students should have little problem locating an adequate explanation for the operation of a dual-slope ADC.

In order to answer this question, students must have a good grasp of how the summing integrator works. Discuss with them how the feedback loop’s “goal” is to maintain the integrator output at the reference voltage (V_ref), and how the 1-bit ADC can only make adjustments to the integrator’s output by driving it upward or downward by the same analog quantity every clock pulse.

With little effort, your students should be able to see that sampling twice as many bits in the PDM bitstream adds one more bit of resolution to the final binary output. Such is the nature of so many circuits: that optimization of one performance parameter comes at the expense of another.

Students may question how two (or more!) different decimation results can occur from the same bitstream, especially as shown in the answer for the 7-bit groupings. The answer is two-part: first, the bitstreams I show are not all perfectly repetitive. Some change pattern (slightly) mid-way, which leads to different pulse densities in different sections. The second part to this answer is that the nature of decimation by grouping will inevitably lead to differing results (even when the pattern is perfectly repetitive), and that this is the converter’s “way” of resolving an analog quantity lying between two discrete output states. In other words, a pair of decimated values of “4” and “5” (100₂ and 101₂, respectively) from a perfectly repetitive bitstream suggests an analog value lying somewhere between the discrete integer values of “4” and “5”. Only by sampling groups of bits equal to the period of the PDM repetition (or integer multiples of that repetition) can the digital output precisely and constantly equal the analog input.