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Memory Devices
18 questions By Tony R. Kuphaldt
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Question 10 of 18
Suppose you need to store a text message in digital memory, consisting of 7500 ASCII characters. What is the most logical memory organization (addresses × data lines) to do this? How many address bits would be needed to store these 7500 characters?
Reveal answerIdeal memory organization: 8k × 8, thirteen address bits required.
Notes:Be sure to ask your students how they calculated 13 bits for the address. Of course, there is the trial-and-error method of trying different powers of two, but there is a much more elegant solution involving logarithms to find the requisite number of bits.
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Question 11 of 18
Suppose you need a memory array with 1k × 8 organization, but all you have on hand are 1k × 4 memory chips. Show how you could connect two of them to form the desired array:
Reveal answer
Follow-up question: a common mistake made by students when they “expand” the data bus width of a memory array is to parallel the output lines (in the same way that the address lines are shown paralleled here). Why would this be wrong to do? What might happen to the memory chip(s) if their data lines were paralleled?
Notes:Be sure to spend some time discussing the common mistake referenced in the follow-up question. This is something I’ve seen more than once, and it reveals a fundamental gap in understanding on the part of the mistaken student. What students are prone to do is try to memorize the sequence of connections rather than really understand why memory array expansion works, which leads to errors such as this.
Note that the answer to “what might happen” depends on whether the first operation is a read, or a write.
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Question 12 of 18
Suppose you need a memory array with 2k × 4 organization, but all you have on hand are 1k × 4 memory chips. Show how you could connect two of them to form the desired array:
Reveal answer
Follow-up question: which of the two memory chips shown here stores the first 1024 addresses, and which one stores the next 1024 addresses? How can you tell?
Challenge question: as you can see, the expansion in addresses comes at the expense of losing the ability to simultaneously disable both memory chips. Add whatever logic gates are necessary to this circuit to provide a “global” [CS] line for the 2k × 4 memory array.
Notes:Be sure to spend some time discussing the follow-up question. Once again, I’ve noticed students are prone to memorizing the connection pattern rather than take the time to figure out why the chips are connected as they are.
