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Category: System On Chip IP Cores (3)

NoCmodel - Python Module for Network-on-Chip Modeling

NoCmodel - Python Module for Network-on-Chip Modeling

NoCmodel is a Python module for Network-on-Chip modeling, with add-ons for simulation (functional or RTL) and code generation (initially VHDL).…

License : LGPL
Language : Other
SardMIPS - Synthesizable Parametric IP Core of 32-bit RISC Processor

SardMIPS - Synthesizable Parametric IP Core of 32-bit RISC Processor

Embedded MIPS R2000 It's a synthesizable parametric IP core of 32 bit RISC processor supporting full MIPS R2000 ISA, by using SystemC HDL. An…

License : GPL
Language : Other
WISHBONE to OPB Bus Interface Wrappers

WISHBONE to OPB Bus Interface Wrappers

OPB ->WISHBONE and WISHBONE->OPB bus interface wrappers OPB Bus to WISHBONE bus and WISHBONE bus to OPB bus interface wrappers. The Interface…

Language : Other