Technical Article

Introduction to Class A Power Amplifiers: The Common-Emitter PA

December 22, 2023 by Dr. Steve Arar

RF amplifier design is a challenging task, involving trade-offs between linearity, efficiency, gain, and output power. Here, we examine how a common-emitter circuit can, or can't, function as a power amplifier.

The preceding articles of this series discussed small-signal amplifiers, which are usually designed for gain and linearity rather than power delivery. If the circuit that follows it has a purely capacitive input impedance, a small-signal amplifier might provide a specific voltage or current gain without delivering any significant power to its actual load. Since small-signal amplifiers don’t deal with high power levels, power-handling capacity, and power efficiency are also not among their main design requirements.

Over the next few articles, we’ll discuss something rather different: RF power amplifiers. Power amplifiers (PAs) appear at the output of transmitters and are responsible for delivering RF power to the antenna. We can expect the peak AC current of a power amplifier to be in the range of 200 mA or higher—certainly not a small signal.

This leads us to an important distinction between power amplifiers and linear small-signal amplifiers. The AC current of a PA is typically comparable with its quiescent bias current. Since PAs handle large amounts of AC current, and large bias current means a less linear operation, we can therefore expect PAs to be substantially nonlinear. Even Class A power amplifiers—the most linear type of PA, and the primary topic of this article—are commonly designed to provide a peak AC current equal to the transistor’s bias current.

We’ll start our study of Class A power amplifiers by examining the problems of power efficiency and power-handling capacity, both of which are of primary importance in PA design. We’ll then see if we can solve these problems by using a common-emitter stage as a power amplifier. After we work through some calculations, we’ll end by introducing the inductively-loaded Class A power amplifier.

 

Power Efficiency and Power-Handling Capacity

Because they’re designed to provide a large amount of power at the output, PAs are the most power-hungry block in the RF transceiver. If a PA delivering 30 kW to the antenna is only 50% efficient, for example, the amplifier itself will burn 30 kW. This can be a rather challenging thermal management problem.

Efficiency is a major concern, whether the PA is delivering tens of watts to the antenna of a broadcast transmitter or a few watts to the antenna of a portable communications device. Even in a low-power, portable application, a low-efficiency PA is less effective at producing usable output power—in point of fact, the PA will waste the available power provided by the battery. With a more efficient PA, battery-powered device usage can last longer.

Another PA design challenge arises from the large signals power amplifiers typically deal with. Consider a portable device that delivers 1 W of RF power to a 50 Ω antenna. This requires providing a peak-to-peak voltage swing of 20 V and peak current of 200 mA through the antenna. As you can see, even in this low-power application, transistors have to deal with high voltage and current levels to deliver the required amount of RF power at the output.

Meanwhile, in a higher-power application, the active devices have to deal with far greater amounts of voltage and current. Transistors are limited in regard to the maximum voltage and current levels they can handle, as well as in the maximum power they can burn without being damaged, so this can be problematic.

 

Can We Use a Common-Emitter Amplifier as a PA?

Let’s examine the possibility of using a common-emitter (or common-source) stage as a PA. Can we efficiently provide a large amount of output power simply by using a large enough transistor? Assume that the common-emitter stage shown in Figure 1 is to deliver 1 W to a 50 Ω load resistance (RL).

 

Circuit diagram of a common-emitter stage.

Figure 1. Common-emitter amplifier.

 

For the circuit in Figure 1 to be used as a PA, we clearly need to use a power transistor that’s capable of dissipating anywhere from a few watts to tens of watts without being damaged. However, the primary question is still how to maximize the circuit’s output power.

The product of the load's voltage and current determines the delivered power. To achieve maximum output power, the bias point should therefore be chosen to maximize the load’s voltage and current swing. The maximum swing is achieved when the transistor is biased in the middle of its active region. To find the appropriate bias point, we write a KVL equation for the collector branch:

$$v_{CE}~=~V_{CC}~-~R_{L}i_{C}$$

Equation 1.

 

where:

iC is the total collector current

vCE denotes the total voltage between the collector and emitter terminals, including both DC and AC components.

This equation gives us the AC load line of the circuit, which is also plotted in Figure 2. Any possible value of iC and the corresponding vCE fall on the AC load line.

 

AC load line of a common-emitter amplifier.

Figure 2. AC load line of the common-emitter circuit. The bias point (ICQ and VCEQ) can be found at the intersection of the two dotted lines.

 

In our simple example, the AC and DC load lines are the same. This makes determining the voltage and current limits easy—when the transistor is in cutoff (iC = 0), the whole supply voltage therefore appears between the collector and emitter terminals (vCE = VCC). On the other hand, for a saturated transistor, a very small voltage drop (typically 0.1 V) appears between the collector and emitter terminals. Neglecting this small voltage drop, we find the maximum value of the collector current:

$$i_{C}~=~\frac{V_{CC}}{R_{L}}$$

Equation 2.

 

The AC load line shows the current and voltage limits in the circuit. By superimposing the characteristic curves of the specific type of transistor being employed (BJT, FET, etc.) on the AC load line, we can easily determine when the signal exceeds the linear range of the transistor.

To have maximum swing, we choose the bias point (ICQ and VCEQ) in the middle of the AC load line. ICQ is the quiescent collector current:

$$I_{CQ}~=~\frac{V_{CC}}{2R_{L}}$$

Equation 3.

 

and VCEQ is the quiescent collector-emitter voltage:

$$V_{CEQ}~=~\frac{V_{CC}}{2}$$

Equation 4.

 

Therefore, the peak AC current flowing through RL is:

$$i_{c, max}=\frac{V_{CC}}{2R_{L}}$$

Equation 5.

 

In other words, in the case of maximum output power, we can assume that the collector current consists of a bias current of ICQ and a sinusoidal current component of amplitude ic,max:

$$i_C~=~I_{CQ}~+~i_{c,max} \sin(\omega t)$$

Equation 6.

 

where ⍵ is the frequency of the AC signal.

 

Calculating Power Efficiency

The power delivered to the load has two components: the DC power from the bias current and the AC power we wish to maximize. Since we know the peak AC current of the collector (ic,max), we can calculate the average value of the AC power delivered to the load as:

$$\begin{eqnarray} P_L ~=~\frac{1}{2}R_{L}i_{c,max}^2 &~=~& \frac{1}{2} ~\times~ R_{L} ~\times~ \left(\frac{V_{CC}}{2R_{L}}\right)^2 \\ &=&~ \frac{V_{CC}^2}{8R_L} \end{eqnarray}$$

Equation 7.

 

Note that this is the maximum AC power of the load. When an AC signal is not present, zero AC power is delivered to the load.

We can calculate the average power delivered by the supply voltage using the following equation. Equation 6 helps us create the more complicated version on the right, which will prove useful shortly:

$$P_{CC} ~=~\int_{T}^{} V_{CC}i_C~=~\int_{T}^{} V_{CC}\big ( I_{CQ}~+~i_{cm} \sin(\omega t) \big )$$

Equation 8.

 

where T is the period of the signal.

The average value of a sinusoidal term over one period is zero, so Equation 8 simplifies to:

$$\begin{eqnarray} P_{CC} ~=~V_{CC}I_{CQ}~&=&~V_{CC} ~\times~ \frac{V_{CC}}{2R_{L}} \\ &=&~ \frac{V_{CC}^2}{2R_L} \end{eqnarray}$$

Equation 9.

 

The formula for ICQ can be found in Equation 3.

Finally, using Equations 7 and 9, the maximum efficiency of the amplifier is calculated as:

$$\begin{eqnarray} \eta ~&=&~ \frac{ \text{AC Power Delivered to the Load}}{ \text{Power Delivered by the Supply}} \\ &=& ~\frac{V_{CC}^2 /8R_{L}}{V_{CC}^2 /2R_L}~=~25 \% \end{eqnarray}$$

Equation 10.

 

This means that the supply must provide 4 W in order to deliver 1 W to the load. Part of the extra 3 W is lost in the transistor; the rest is lost as DC power in RL. In practice, the achievable efficiency can be much less than 25%.

Now that we know how to calculate the maximum efficiency, let’s find the optimum load.

 

Calculating the Optimum Load

Taken together, Equations 3 and 4 show that a certain relationship must exist between RL and the transistor’s bias point for the transistor to achieve maximum output power. In other words, for given bias conditions, there is an optimum load that maximizes the output power.

Based on the maximum power transfer theorem, we might expect the optimum RL to depend on the output impedance of the transistor. Instead, it only depends on VCC and the bias point. This is actually an interesting (and sometimes confusing) point, but the more detailed explanation it deserves will have to wait for a different day. For now, let’s consider the common-emitter circuit in Figure 3.

 

Common-emitter amplifier with a 12 V supply voltage and a 750 mA quiescent current.

Figure 3. Common-emitter amplifier with a supply voltage of 12 V and a quiescent current of 0.75 A.

 

Given a supply voltage of VCC = 12 V and a quiescent current of ICQ = 0.75 A, what value of RL will yield the highest output power?

We obtain the formula for optimum load resistance by rewriting Equation 3 to solve for RL.

$$I_{CQ}~=~\frac{V_{CC}}{2R_{L}}~~ \Rightarrow~~ R_{L}~=~\frac{V_{CC}}{2 I_{CQ}}$$

Equation 11.

 

For the supply voltage and quiescent current values given above, this works out to:

$$R_{L}~=~\frac{12}{2~\times~ 0.75}~=~8~\Omega$$

Equation 12.

 

Figure 4 shows the load line for three different load resistance values: RL = 4 Ω, 8 Ω, and 13.33 Ω. This figure helps us to visualize how different load resistances for a given quiescent current can produce differing voltage swings, and consequently differing output power values.

 

Load lines for three different load resistance values, including the optimum.

Figure 4. Load lines for three different load resistance values: RL = 4 Ω (purple), RL = 8 Ω (blue), and RL = 13.33 Ω (orange).

 

The results:

  • With RL = 4 Ω, we observe that ICQ = 0.75 A is achieved at VCEQ = 9 V. In this case, the peak-to-peak swing is 6 V (half the swing we have with RL = 8 Ω).
  • The optimum value, RL = 8 Ω, leads to a DC collector-emitter voltage of VCEQ = 6 V, which is in the middle of the load line.
  • RL = 13.33 Ω leads to VCEQ = 2 V, which again produces a peak-to-peak swing smaller than the optimum value.

We began the calculations portion of this article by asking if we could use a simple common-emitter stage to efficiently deliver large amounts of output power. It would appear that the answer is “no.” But why is this?

 

Disadvantages of the Common-Emitter Stage

With a simple common-emitter stage, the bias current always flows through the load. As a result, an amount of DC power equal to RLICQ2 is always wasted in the load just to bias the transistor. Using Equation 7, you can verify that this DC power is twice the maximum AC power we can deliver to the load.

This is one reason why the circuit exhibits poor efficiency. Furthermore, what we calculated is the maximum possible efficiency. The efficiency will drop even more if the AC signal is lower than the maximum swing.

Another disadvantage of the circuit is that it provides a relatively smaller voltage swing for a given supply voltage. For example, consider the problem of delivering 1 W of RF power to a 50 Ω antenna. As we mentioned above, this requires providing a peak-to-peak voltage swing of 20 V, and a peak current of 200 mA through the antenna.

As the AC load line in Figure 2 shows, the maximum peak-to-peak swing is equal to VCC. We therefore need a supply voltage greater than 20 V to provide 1 W to the antenna! Many portable devices use far smaller supply voltages.

 

The Inductively-Loaded Class A Power Amplifier

Figure 5 shows the basic diagram of a more practical Class A amplifier. This amplifier circumvents some of the above issues by using an inductive load and a DC blocking capacitor.

 

Circuit diagram of an inductively-loaded Class A amplifier.

Figure 5. Basic diagram of an inductively-loaded Class A amplifier.

 

Let’s examine the labeled portions of the above model.

  • RL is the resistor. It represents the actual load we wish to deliver power to.
  • L1 is the inductor. It’s large enough to act as an AC open circuit at the frequency of interest—we call such an inductor an “RF choke.”
  • VCC is the supply voltage. As we’ll see in the next article, an inductively-loaded stage can have a symmetrical voltage swing that’s double the value of VCC.
  • Req is the optimum load that maximizes the output power.
  • C1 is the capacitor. It blocks DC current, but acts as an AC short circuit at the frequency of interest.

A matching network is used to transform RL into Req. Since matching networks are almost always implemented using reactive components (inductors and capacitors), power delivered to the input of the matching network is dissipated in RL. To prevent any DC dissipation in RL, the collector is connected to the matching network through C1. As mentioned above, C1 serves to block DC current.

In the next article of this series, we’ll continue our discussion of inductively-loaded Class A amplifiers in greater depth.

 

Featured image used courtesy of Adobe Stock; all other images used courtesy of Steve Arar

1 Comment
  • S
    Setel December 29, 2023

    The transistor in fig. 5 will burn out without h.f. drive.

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