Switched Capacitor Circuitry

A 4.7 μF capacitor (C_i) is charged to a voltage of 4 volts, then connected to the inverting input of an operational amplifier (with a 10 μF feedback capacitor, C_f). What happens to the voltages across C_i and C_f? Explain your answer in detail.

Many switched capacitor circuits require non-overlapping, two-phase clock signals. Shown here is a schematic diagram of a gate circuit that converts a single clock signal into two complementary, non-overlapping clock signals:

Assume that the only gates possessing propagation delays are the double-NOT gates (inside the dotted boxes), whose sole purpose it is to provide a short time delay in the feedback signals. Draw a timing diagram showing the two-phase clock signals (φ₁ and φ₂) in relation to the input clock waveform, and be prepared to explain how and why this circuit works:

The fact that switched capacitor networks can behave equivalently to resistors is exploited in a variety of integrated circuits. At first, this may seem strange, as switched capacitor networks generally require at least two switching transistors and a two-phase, non-overlapping clock (in addition to the capacitor itself) in order to function, which seems like a lot of peripheral circuitry compared to a single resistor. What possible advantage is there to using switched capacitor networks in integrated circuits instead of resistors? Support your answer with research, if possible.