Or try an example search: AES128
C code for generating a stand-alone population counter with user-defined size (number of input bits) and latency (number of clock cycles) in VHDL.
This project implements a parameterized Reed Solomon decoder for use in OFDM wireless systems. Source code provided in C++ (trunk/cpp-source) and…
Please write a description of the project here. It is used as a MetaTag (search engines looks at this).
LFSR Counter Generator is a command-line application that generates Verilog or VHDL code for an LFSR counter of any value up to 63 bit wide. The…
CRC Generator is a command-line application that generates Verilog or VHDL code for a parallel CRC of any data width between 1 and 1024 and…
n/a
EziDebug is an easy-to-use versatile logic simulation tool for verification and debugging of digital circuits. It supports inserting scan chains in…
Converts Raspberry Pi into a JTAG programmer (STAPL protocol). Supports two JTAG chains through 26-pin RPi GPIO P1 connector. The TCK rate is…
Constrained random testing enables us to cover many more system behaviors through random input variations, random fault injections, and automatic…
Facebook
Google
GitHub
Linkedin
