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The ao486 is an x86 compatible Verilog core implementing all features of a 486 SX. The core was modeled and tested based on the Bochs software x86…
The aoR3000 is a MIPS R3000A compatible core capable of booting the Linux kernel version 3.16 in about 3 seconds and with a rating of 48.74…
A classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a 1024 depth branch prediction buffer, a 2KB direct-mapped…
Introduction The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog. It is compatible with Texas Instruments' MSP430…
This project provides interface logic and assembler routines, giving PicoBlaze (TM) embedded soft-uC the ability to access wishbone systems or…
This project is a soft processor core compatible with 586 instruction set. The processor core has AXI4 interface and uses XILINX AXI4 IPs such as…
mmu180 is a MMU (memory mananagement unit) designed per original specifications of Zilog's Z180 family of processors (including Hitachi…
The TV80 is an 8-bit Z80-compatible microprocessor core, written in Verilog. It is based on Daniel Wallner's VHDL T80 core. Features - executes…
Z80/Z180 compatible processor softcore. Based on Y80 project described in the book 'Microprocessor Design Using Verilog HDL' of Monte…
A Verilog implementation of the Infocom Z-Machine V3. The spec the Z3 follows is http://inform-fiction.org/zmachine/standards/z1point0index.html.…
The OpenCores ao68000 IP Core is a Motorola MC68000 binary compatible processor. Introduction July 2011: Project copied to…
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