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Category: All IP Cores (3)

SPI Slave Wishbone Master Controller

SPI Slave Wishbone Master Controller

If a FPGA or CPLD needs to be coupled to a microcontroller often a fast interface is needed. Many controllers do not provide an external…

License : LGPL
Wishbone Version : B.4
Language : VHDL
Avalon to Wishbone Bridge

Avalon to Wishbone Bridge

AVALON/WISHBONE Bridge This is an Avalon to WishBone Bridge. Avalon is a bus standard mainly used in Altera(Now Intel) Tools. Wishbone as every one…

License : LGPL
Wishbone Version : B.4
Language : Verilog
Wupper: PCIe DMA Engine for Xilinx Virtex-7 FPGA Gen3 Integrated Block

Wupper: PCIe DMA Engine for Xilinx Virtex-7 FPGA Gen3 Integrated Block

Wupper is designed by Nikhef (Amsterdam, The Netherlands) for the CERN ATLAS / FELIX project. Its main purpose is to provide a simple Direct Memory…

License : LGPL
Wishbone Version : B.4
Language : VHDL