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VHDL Memory Cores Module

VHDL Memory Cores Module

Check the memory cores site for more documentation at Jamil Khatib site. Status - VHDL codes are stable and available on the CVS - Some cores need…

Memory Sizer : Access Up to 256 Bits Wide

Memory Sizer : Access Up to 256 Bits Wide

The memory_sizer project is designed to automatically handle accesses to and from memory. It does not handle refreshing DRAM at all, but it does…

Ogg Vorbis Encoder/Decoder for Virtex-II Pro FPGA

Ogg Vorbis Encoder/Decoder for Virtex-II Pro FPGA

Status I just started reading the Ogg Vorbis spec. and I'm seeing if other people are interested.

OPB PSRAM Controller

OPB PSRAM Controller

The OPB PSRAM-Controller connect a Pseudo-Staic-RAM, also named CellularRAM™ to the OPB-Bus. Features Design - max. 80 Mhz Memory Clock for a…

License : GPL
Language : VHDL
Open FreeList Module

Open FreeList Module

Open FreeList Readme General Description The Open FreeList module is used to manage a set of variable sized packets inside a fixed memory block.…

License : LGPL
Language : Verilog
Versatile Memory Controller

Versatile Memory Controller

Overview This is a modular memory controller supporting different types of memories. Initial design will have support for SDR SDRAM. Upcoming…

License : LGPL
Language : Verilog
Parametrized FIFO based on SRL16E

Parametrized FIFO based on SRL16E

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : VHDL
Scratch DDR SDRAM Controller VHDL

Scratch DDR SDRAM Controller VHDL

DDR SDRAM controller core targeted at the mt46v32m16 chip on the Spartan3e Starter Board. The testbench synthesizes and runs on the targeted…

License : LGPL
Language : VHDL
Single Port ASRAM in VDHL

Single Port ASRAM in VDHL

The main purpose of this project was two-fold. The first purpose was to implement a client-server test architecture based on Bergeron's work in…

License : LGPL
Language : VHDL
Verilog Single Port RAM to 3 Port RAM Wishbone Wrapper

Verilog Single Port RAM to 3 Port RAM Wishbone Wrapper

This is a wrapper for an inferred single port RAM, that converts it into a Three-port RAM with one WISHBONE slave interface for each port. Very…

License : LGPL
Language : VHDL
SRL Feature FIFO in Xilinx FPGAs

SRL Feature FIFO in Xilinx FPGAs

Synchronous FIFO's based upon the SRL feature found in Xilinx FPGA's. Built to be small. In a Spartan 3, the 8 bit wide , 16 bit deep FIFO…

License : LGPL
Language : VHDL
SSRAM Interface Memory Core

SSRAM Interface Memory Core

The 'SSRAM interface core' is a collection of designs for easy integration of synchronous srams (ZBT srams) in your designs. Core…

USB NAND Flash Reader

USB NAND Flash Reader

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : C/C++
Versatile FIFO Designs Using Verilog

Versatile FIFO Designs Using Verilog

The FIFO implementation outlined in this document can easily be configured to suit the following asynchronous FIFO with different clock domains for…

License : LGPL
Language : Verilog
Wishbone Asynchronous Memory Bridge

Wishbone Asynchronous Memory Bridge

This project provides a bridge between asynchronous external memory interfaces found on many processors and a WishBone bus. It is being used on the…

License : LGPL
Language : Verilog
Wishbone DDR3 SDRAM Controller Verilog

Wishbone DDR3 SDRAM Controller Verilog

The purpose of this core is to provide a GPL wishbone core capable of commanding a DDR3 memory, such as the one used on Digilent's Arty board,…

License : GPL
Language : Verilog
Wb Size Bridge for 32-bit Wishbone Interface

Wb Size Bridge for 32-bit Wishbone Interface

Overview This IP provides a 8-bit or 16-bit bridge for a 32-bit WishBone interface. There is no buffering. The 32-bit transaction is delayed until…

Language : Verilog
Wishbone Interface for SPI FLASH

Wishbone Interface for SPI FLASH

This module uses an interface to SPI serial FLASH memory devices to allow reading/writing/erasing of the FLASH. It includes a state machine that…

License : LGPL
Language : VHDL
ZBT SRAM Controller Wishbone Rev B.3 Compatible

ZBT SRAM Controller Wishbone Rev B.3 Compatible

This is a ZBT SRAM controller which is Wishbone rev B.3 compatible (classic + burst r/w operations). PLEASE NOTICE THAT THIS CORE IS LICENSED UNDER…

Language : VHDL
VHDL 8254 Timer Using Synchronous Processor Interface

VHDL 8254 Timer Using Synchronous Processor Interface

a VHDL version of the Intel 8254 timer. Note: uses a synchronous (Wishbone) processor interface, rather than an asynchronous of the Intel 8254.…

Language : VHDL