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Category: System On Chip IP Cores (5)

PSS (Programmable Supervisor For Systems-on-Chip)

PSS (Programmable Supervisor For Systems-on-Chip)

PSS (Programmable Supervisor for Systems-on-chip) is a soft IP core that targets to provide the basic means for conducting service operations…

License : BSD
Language : Verilog & VHDL
ECO32 32-bit RISC Microprocessor SoC

ECO32 32-bit RISC Microprocessor SoC

The ECO32 system is a microprocessor system-on-chip, consisting of a 32-bit CPU and several controllers for peripheral devices (keyboard, character…

License : BSD
Language : Verilog
aoOCS - Wishbone Amiga OCS SoC Implementation

aoOCS - Wishbone Amiga OCS SoC Implementation

The OpenCores aoOCS SoC is a Wishbone compatible implementation of most of the Amiga Original Chip Set (OCS) and computer functionality. aoOCS is…

License : BSD
Language : Verilog
System-On-Chip Based on Bare Rocket-chip (RISC-V ISA)

System-On-Chip Based on Bare Rocket-chip (RISC-V ISA)

Common top-level structure. * CPU: Single core "Rocket-chip": 64-bits CPU (RISC-V ISA) with L1/L2 caches, MMU, TLBs, 128-bits data bus…

License : BSD
Language : VHDL
Internal Communication Bus for FPGA

Internal Communication Bus for FPGA

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : BSD
Language : VHDL