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Category: Uncategorized IP Cores (32)

Configurator

Configurator

This application parses a Verilog define file and presents a GUI to the user

License : LGPL
Language : Verilog
Gsc

Gsc

Description of project.. Features - feature1 - feature1.1 -feature1.2 -feature2

License : GPL
Language : Verilog
2D Game Console on Altera DE2-115

2D Game Console on Altera DE2-115

A platform for execute simple games, with graphics in two dimensions, implemented on Altera DE2-115 development board. • Compatible with Sega…

License : LGPL
Language : Verilog & VHDL
Adjustable Frequency Divider

Adjustable Frequency Divider

Usage and Operation In order to operate the circuit correctly it must first be reset (asynchronously). Below is a timing diagram that illustrates…

License : LGPL
Language : Verilog
Programmable Sound Generator AY-3-8910 Compatible Module

Programmable Sound Generator AY-3-8910 Compatible Module

This module is software compatible with the PSG (Programmable Sound Generator) AY-3-8910. It can be used to produce music.

License : GPL
Language : Verilog
Avalon to Wishbone Bridge

Avalon to Wishbone Bridge

AVALON/WISHBONE Bridge This is an Avalon to WishBone Bridge. Avalon is a bus standard mainly used in Altera(Now Intel) Tools. Wishbone as every one…

License : LGPL
Wishbone Version : B.4
Language : Verilog
BU PACMAN Game with Advanced Digital Design Using Verilog

BU PACMAN Game with Advanced Digital Design Using Verilog

This is for the final project of EC551 Advanced Digital Design using Verilog, a course offered in Boston University. It's basically the classic…

License : GPL
Language : Verilog
Bubble Sort Module in Verilog

Bubble Sort Module in Verilog

simple fast bubble sort module in verilog

License : LGPL
Language : Verilog
DNA Sequence Alignment Accelerator

DNA Sequence Alignment Accelerator

This is an easily configurable systolic array of processors to compute the optimal alignment between two DNA sequences. It supports affine gap…

License : LGPL
Language : Verilog
Cray-2-Reboot for FPGAs

Cray-2-Reboot for FPGAs

Files also located at: https://github.com/DarkwaveTechnologiesCray-2-Reboot The goal of this project is to make a clock and gate equivalent…

License : LGPL
Language : Verilog
Verilog Code LCD Block

Verilog Code LCD Block

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : Verilog
Interrupt Controller 68000

Interrupt Controller 68000

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : Verilog
OPL3 20 - Yamaha OPL3 (YMF262) FM Synthesizer Chip

OPL3 20 - Yamaha OPL3 (YMF262) FM Synthesizer Chip

Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer chip. Design is complete and working on the Digilent ZYBO…

License : LGPL
Language : Verilog
PSG16 Audio Interface Circuit

PSG16 Audio Interface Circuit

PSG32 is an audio interface circuit (sound interface device) for use within a programmable system to interface the system to an audio output. It…

License : LGPL
Language : Verilog
Pulse Width Modulator with 16-bit Main Counter

Pulse Width Modulator with 16-bit Main Counter

Pulse Width Modulator Features • Work as one PWM or one timer. • 16 bits main counter. • PWM/Timer can choose between Wishbone…

License : LGPL
Language : Verilog
PWM audio controller With Integrated Timer

PWM audio controller With Integrated Timer

This is a very simple PWM audio controller with an integrated timer. It has been designed for use with Digilent's Audio Amplifier, and the…

License : GPL
Language : Verilog
Implementation of Round Robin Arbiter in Verilog Code

Implementation of Round Robin Arbiter in Verilog Code

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : GPL
Language : Verilog
Quadrature Rotary Encoder and Low-pass Filter

Quadrature Rotary Encoder and Low-pass Filter

Module receives A and B quadrature signals from incremental angular sensor and counts relative angular position. Angular resolution is 4 counts per…

License : LGPL
Language : Verilog
Full Duplex Support Simple AC’97 Controller

Full Duplex Support Simple AC’97 Controller

This core is part of the Milkymist System-on-Chip, the most advanced open source SoC for interactive multimedia applications. 16-bit 48kHz stereo…

License : GPL
Language : Verilog
Simple Linear Digital Automatic Gain Control (AGC)

Simple Linear Digital Automatic Gain Control (AGC)

Simple linear digital automatic gain control. More info: https://www.embedded.com/print/4214571

License : LGPL
Language : Verilog