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An n-width Galois LFSR generator written in MyHDL with max-cycle tap positions for selected widths. An table of taps for selected widths is used to…
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A FPGA development board based on EP2C35F672, with SDRAM and flash .
Griva Basic 1.2v - FPGA development kit ,, , Highlights , , , , , , , , , * Xilinx Spartan3E XS3S250E or XC3S500E -PQG208 , , , , , , , , , , , , ,…
Project to create generic emulator/debugger/analyzer with on-the-fly reprogrammable firmware on Artec Dongle II board (containing Altera Cyclone…
A SystemC/Verilog synthesizable MD5 hash core. This work is given by Universidad Rey Juan Carlos (Spain) For more info about our projects visit…
Cascaded integrator-comb (CIC) digital filters are computationally efficient implementations of narrowband lowpass filters and are often embedded…
The Advanced Debug Interface is a suite of IP cores and software programs designed to allow a developer to download code to a target CPU in a…
myBlaze is a synthesizable clone of the MicroBlaze Soft Processor written in myHDL ( http://www.myhdl.org ). It started as a translation of MB-Lite…
NoCmodel is a Python module for Network-on-Chip modeling, with add-ons for simulation (functional or RTL) and code generation (initially VHDL).…
This project shows a 4-bit open system done with Quartus II v12
Uart2BusTestBench is implemented using Universal Verification Methodology to perform the functional verification to the RTL design released by Moti…
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