This is a modular IO component. With this modular IP design tou can get multiple (by default up to 8) IO channels. Each channel has a RX and TX…
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Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read and Write cycles, 8-bit Memory Read/Write…
Implements a 16550/16750 UART. The UART core is fully based on another OpenCores project: UART_16750 by Sebastian Witt. Please find there the…
The ORSoC Graphics Accelerator can: Draw Lines. Draw Filled or Textured Rectangles. Draw Filled, Interpolated or Textured Triangles. Draw Filled…
Wrimm provides Wishbone interconnect functionality, multi-master arbitration, multi-slave partial address deccoding and bus multiplexing. Wrimm…
This package consists of multiple parts, a uart connection a uart to intruction converter and an 8 bit wishbone controller. The uart connection is…
A fabric coprocessor module (FCM) for the PowerPC 405 CPU providing code execution timestamp, allowing to measure precisely CPU code execution times.
The Xgate Co-processor Module, Xgate, is a 16 bit programmable RISC processor that is managed by a host CPU to reduce the host load in handling…
Cores are generated from Confluence; a modern logic design language. Confluence is a simple, yet highly expressive language that compiles into…
Overview YANU (Yet Another Niosii Uart) has been built from scratch with the efficiency in mind in term of CPU load. A complete uCLinux TTY driver…
This is a single precision floating point unit. It is fully IEEE 754 compliant. It can currently perform Add/Sub, Mul and Divide operations, as…
AES (Advanced Encryption Standard) is a specification published by the American National Institute of Standards and Technology in 2001, as FIPS…
Simple AES (Rijndael) IP Core. I have tried to balance this implementation and to trade off size and performance. The goal was to be able to fit in…
The JT51 is an 8-channel FM sound synthesiser. Each channel is composed of four operators that can be arranged in eight different connections.…
WishboneAXI This project is a universal, configurable Wishbone AXI bridge together with Xilinx IP wrapper, which makes it suitable for Block Design…
Here you can find two different implementations of AES encryption algorithm: - A 128 bits AES algorithm focusing on very low area applications. - A…
The NIST has selected cipher Rijndael as AES on October 20, 2000 based on the combination security, performance, efficiency, ease of implementation…
Consecutive AES core Description of project.. Features - AES encoder - 128/192/256 bit - AES decoder - 128/192/256 bit Status - Key Expansion added…
This Core implements the Advanced Encryption Standard (Rijndael Algorithm) according to the NIST standard as documented in FIPS-197. This AES core…
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