This is a fully synchronous (single clock domain, no asynchronous resets) UART with a FIFO buffered cpu interface and a SystemVerilog transaction…
The UART to SPI IP Core include a simple command parser that can be used to access an internal bus of SPI via a UART interface. This IP can be used…
Introduction Transmitter and receiver in FPGA for converting UART to/from audio fiber optics. Photo of an assembled board with annotation It is…
Have you ever needed a fast and easy way to test your new FPGA board? You know you have all the interfaces but it will take time to finish the…
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Implements a 16550/16750 UART core. Features - Full synchronous design - Pin compatible to 16550/16750 - Register compatible to 16550/16750 -…
uart6551 is a 6551 register compatible uart core. It is a 32-bit bus peripheral and features 32-bit wide registers with additional functionality.…
This is a simple UART implementation with intention to valid ASIC learning and use it on simple applications. The environment was rebuild with…
The UDP/IPv4 for 10 G Ethernet IP core, implements mandatory parts of UDP, IPv4 and Ethernet (MAC) protocols. It is minimal implementation of…
VHDL implementation of a UDP/IP core! Area-optimized for direct PC-FPGA communication! An advanced/versatile version of the core is included in the…
=== What's "vSPI"? === vSPI is a Verilog implementation of an SPI slave. Think of it as a very fast serial port. It can reliably…
A USB FS Host simulation environment (test bench) in VHDL. This USB FS test bench has been used with the Model Sim VHDL Simulator, however 4 any…
This is a Verilog to VHDL translation of Rudolf Usselmanns USB 1.1 PHY. Since the original design operates with a 48 MHz clock and I required a 60…
USB 1.1 slave/device IP core. Default configuration is 6 endpoints: 1 Control, 1 Isochronous IN, 1, Isochronous Out, 1 Bulk IN, 1 Bulk Out, 1…
This is a USB 2.0 compliant core. USB 2.0 allows data transfers of 480 Mb/s. Because of the high interface speed, an external PHY will be required…
Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a simplified…
USB Peripheral Interface Github: http://github.com/ultraembedded/cores This component is a simple USB Peripheral Interface (Device) implementation…
The Wishbone SD Card Controller IP Core is MMC/SD communication controller designed to be used in a System-on-Chip. The IP core provides a simple…
This core implements the Altera Avalon-MM interface for FTDI FT232H device in FT245 Synchronous FIFO mode. The core has internal FIFOs on the…
USB 1.1 Host Controller This IP core is a cutdown USB host controller which allows communications with full-speed (12mbps) USB devices. The IP is…
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