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Category: All IP Cores (1032)

SPI Slave Wishbone Master Controller

SPI Slave Wishbone Master Controller

If a FPGA or CPLD needs to be coupled to a microcontroller often a fast interface is needed. Many controllers do not provide an external…

License : LGPL
Wishbone Version : B.4
Language : VHDL
SPI Master Receiver for ADC (AD747x)

SPI Master Receiver for ADC (AD747x)

this core represents an minimalistic SPI receiver for ADC like AD747x. one have: - tunable sequence len, loaded data slice of sequence, - shut-down…

License : LGPL
Language : VHDL
SPI Master & Slave Interface in VHDL

SPI Master & Slave Interface in VHDL

This project started from the need to have robust yet simple SPI interface cores written in VHDL to use in generic FPGA-to-device interfacing. The…

License : LGPL
Language : VHDL
SPI Mode-3 Master & Slave Modules in Verilog

SPI Mode-3 Master & Slave Modules in Verilog

This Project provides SPI Mode-3 Master & Slave modules in Verilog HDL. The data width is 8 bits. It is synthesized for Xilinx Spartan 3E,…

License : LGPL
Language : Verilog
SPI GPIO Expanders in Verilog

SPI GPIO Expanders in Verilog

n/a

License : LGPL
Language : Verilog
Standalone SPISlave on Full Icarus Verilog Test Bench

Standalone SPISlave on Full Icarus Verilog Test Bench

spislave is a minimalist spislave IP core that provides the basic framework for the implementation of custom spislave devices. The core provides a…

License : LGPL
Language : Verilog
SPIxIF FIFO Buffer Transmit Receive Data

SPIxIF FIFO Buffer Transmit Receive Data

This project provides a full function SPI master interface. It provides for a FIFO buffered transmit and receive data path. Further, a ninth bit in…

License : LGPL
Language : Verilog
SSP_Slv - A Slave Interface for SSP

SSP_Slv - A Slave Interface for SSP

This project provides a slave interface for a Synchronous Serial Peripheral (SSP) as found on NXP LPC21xx microprocessors. The implementation…

License : LGPL
Language : Verilog
SSP_UART - Full-function UART

SSP_UART - Full-function UART

This project provides a full-function UART. The UART provides direct support for a two-wire or a four-wire RS-232 style full-duplex serial…

License : LGPL
Language : Verilog
4 or 6 Wire Stepper Motor Controller

4 or 6 Wire Stepper Motor Controller

A very simple project for controlling any standard 4 or 6 wire stepper motor. Only difference between 4 and 6 wire mode is the MOSFET driver…

License : GPL
Language : VHDL
SystemC USB 1.1 Function IP Core

SystemC USB 1.1 Function IP Core

This project consists of the translation of the USB 1.1 Function IP Core Verilog code and dependencies, maintained by Rudolf Usselmann, into a…

Language : Other
Wiegand Controller for Communication Protocols

Wiegand Controller for Communication Protocols

Communication controller (transmitter and receiver) that operates on the Wiegand Protocol. Parity checks needed by different Wiegand-based…

License : LGPL
Language : Verilog
16550D UART in SystemVerilog IEEE 1800-2005

16550D UART in SystemVerilog IEEE 1800-2005

RS232 Protocol 16550D uart (mostly supported) - language : systemVerilog IEEE 1800-2005 (Quaruts2-9.1sp1 Support) - scale : fpga cyclone3 800cell,…

License : LGPL
Language : Verilog
TCP IP Core With DHCP

TCP IP Core With DHCP

The stack implements a TCP/IP endpoint (including DHCP). It interfaces with Microchip's ENC28J60 chip which implements the MAC and PHY layers.…

License : LGPL
Language : VHDL
Bidirectional TCP Socket for FPGA

Bidirectional TCP Socket for FPGA

TCP Socket TCP Socket is a TCP/IP stack implementation. The core acts as a server, allowing a remote client to establish a bidirectional TCP socket…

License : Others
Language : Verilog
TDM Controller with 8 Bit Parallel Backend Interface

TDM Controller with 8 Bit Parallel Backend Interface

Features - 8 bit parallel backend interface - Needs external Framer - Supports E1 bit rate and time slots (32 time slots or 32 DS0 channels at bit…

AIC1106 Altera Avalon for TI TLV320AIC1106 PCM Codec

AIC1106 Altera Avalon for TI TLV320AIC1106 PCM Codec

AIC1106-IPcore This is Altera Avalon IP core for TI TLV320AIC1106 PCM Codec With Microphone Amps & Speaker Driver. Git hub project home:…

License : LGPL
Language : Verilog
16550 UART Core for Wishbone SoC Bus Interface

16550 UART Core for Wishbone SoC Bus Interface

uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550…

Non-blocking TDM Digital Switch Core on Xilinx Spartan II

Non-blocking TDM Digital Switch Core on Xilinx Spartan II

The TDM_Switch core is a non-blocking digital switch that has a capacity of 256 x 256 channels at 2.048 Mb/s. Some of the main features are:…

Language : Verilog
8 Bits Tiny SPI Master Controller

8 Bits Tiny SPI Master Controller

This is an 8 bits SPI master controller. It features optional programmable baud rate and SPI mode selection. Altera SPI doesn't support…

License : LGPL
Language : Verilog