While there are many AES cores around, this one is designed with LUT6 based FPGA architecture in mind from day one. The AES Decryption Core for…
Three different implementations of the AES-128 (VHDL).
The AES behavioral model is not an encryption/decryption core, but a tool to facilitate the verification of AES IPs in HDL simulation.…
AltOR32 is an OpenRISC 1000 architecture derived RISC CPU targeted at small FPGAs and contains only the most basic ISA features from the OpenRisc…
Please write a description of the project here. It is used as a MetaTag (search engines looks at this).
Four stage pipeline design working at 361.890MHz on Xilinx's 28nm Kintex 7 speed grade 3 FPGA device. Calculating 4 blocks parallely,…
The AES-128 pipelined cipher module uses AES algorithm which is a symmetric block cipher to encrypt (encipher) information. Encryption converts…
Features - Latency insensitive design - Should be portable to most bus architectures/platforms - Easily amenable to multi-clock domain extension -…
This IP core loads an unsorted, encrypted list of numbers from memory. It then decrypts and sorts the list. Sorting is acheived using a…
General Description I know there are plenty of AES (Rijndael) implementations around. I created my own anyway because I was unhappy with either the…
Bit-serial multiplication on the NIST B-163 curve. This implementation utilizes DSP481E blocks (Artix-7 FPGA).
The module is designed and optimized for Bitcoin hash work on FPGA or ASIC.
Modular multiplication and modular exponentiation play an important role in the most of existing cryptographic systems. In fact these are time and…
BTCMiner is a Bitcoin Miner software which allows you to make money with your ZTEX USB-FPGA Module. Since these FPGA Boards contain an USB…
Camellia block cipher cores. Features The project is composed of different cores: Performance optimized: exploits pipelining in order to maximize…
Funbase project focuses on FPGA-based embedded product development. Immediate drivers are customer driven, networked development and design effort…
The main goal on this research work was to provide a compact hardware CLEFIA structure, while still being able to achieve implementations with…
Crypto-PAn A hardware implementation of Crypto-PAn[1]. The core makes use of a fully pipelined 128-bit AES (Rijndael) cipher engine as the…
VHDL implementation of the classic DES block cipher (iterative architecture).
Simple DES/Triple-DES core. Motivation - A simple DES core - Fast and Small Version - Open Source Compatibility I believe that the core complies to…
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