A hamming encoder and decoder with single-error correcting and double-error detecting capability. The message length can be configured through a…
This project contains files you can use to expand upon the basic IEEE packages you normally use for creating testbenches and RTL code. Features…
Common Design Environment (CDE) is a library of modules that usually require replacement with specific hard macros when the design is retargeted to…
fixed_extensions_pkg is a fixed-point arithmetic package written in VHDL according to the VHDL-2008 update of the standard. It uses VHDL-2008 back-…
Perhaps more of a collection of part than a true library, this is a set of VHDL parts that may be used as a set of building blocks for larger…
A collection of basic building blocks for SystemVerilog AXI4 based projects.
FPGA implementation of deflate (de)compress RFC 1950/1951 This design is implemented in MyHDL (www.myhdl.org) and can be translated to Verilog or…
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About this core This is a collection of commonly used base functions, used in all of ASTRONs other cores. These source files can work in any…
About this core This is a collection of commonly used base functions, used in all of ASTRONs cores that have a DP (based on Avalon) streaming…
MyGPU is a library of large-scale components like FPU units, a processor and auxillary units which can be used to build SoCs, processors, etc. We…
openVeriFLA 2019 - FPGA logic analyzer openVeriFLA 2019 is an FPGA logic analyzer. The host computer software is written in Java, so it is platform…
Feature: • 8/16/32 Configurable SDRAM data width • Wish Bone compatible • Application clock and SDRAM clock can be async •…
This library has functions for generating good quality random numbers in a VHDL testbench environment. The functions will NOT synthesize. Features…
"ratpack" is a rational arithmetic package written in VHDL. Currently, the "ratpack" package implements the following: - the…
This core offers a real-time clock capability to a device. Specific capabilities include 24-hour BCD time, a count down timer, a stop watch, an…
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This project implements a DDR2-SDRAM Controller on a Xilinx Spartan-3A Board Function After a Power on : ================== 1. Init-Sequenz for the…
The srdy-drdy library provides a group of components all built around a common data-transfer protocol. This protocol is used in datapath…
A Verilog HDL library with frequently used functions. Care have been taken to fully support synthesis of all modules. Different versions exist for…
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