This project comprises the VHDL description and configuration script of a configurable IIR filter. The VIIRF can implement any transfer function…
This is a behavioral SystemC model for Polyphase Decimation filters. It can be used as for system design and functional verification. It has been…
This project is a digital signal processing (DSP) implementation of a circuit that provides periodic samples of both sine and cosine waveforms.…
LDPC Encoder for 10GBase-T Ethernet (802.3an). See also http://opencores.orgproject,ldpc_decoder_802_3an,overview (802.3an LDPC Decoder). FILE:…
Cores are generated from Confluence; a modern logic design language. Confluence is a simple, yet highly expressive language that compiles into…
The project describes an IPCore in verilog about binary BCH encoder and decoder. BCH is a popular error correcting code used in storage and…
This C++ program generates VHDL package with hamming encoder and decoder. It also generates a simple testbench that can be used to evaluate the…
The double error correcting (DEC) BCH encoder / decoder IP cores. Features : – allows to correct up to 2 errors. – supports…
Product Code Iterative Decoder An iterative decoder for Product Code, this decoder works for two dimensional product code. Status - Synthesized…
Hamming (7,4) Encoder: This core encodes every 4-bit message into 7-bit codewords in such a way that the decoder can correct any single-bit error.…
PCI express CRC verilog code 16 bit data 32 bit CRC Functional Description Designers commonly use Cyclic Redundacy Codes (CRC) as an alternative to…
• Reed Solomon Decoder (204,188), with T=8. • Input codeword length is 204 bytes and output length is 188 bytes. • Corrects up to 8…
Status - RTL done and design verified using testbench. - Will upload soon. - June 27th 2004, updated. Please click on 'Downloads' (top…
Specifications - Hard-decision decoding scheme - Codeword length (n) : 31 symbols - Message length (k) : 19 symbols - Error correction capability…
The Advanced Debug Interface is a suite of IP cores and software programs designed to allow a developer to download code to a target CPU in a…
This core implements Reed-Solomon decoder for the 8-bit wide symbols. The core is designed to occupy fewer amounts of logic blocks, be fast and…
Reed Solomon (5, 3) Encoder-Decoder in GF(256) - Symbol width : 8-bits. - Encodes every 3-byte message into 5-byte codewords. - Capable of…
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This project features a double binary, DVB-RCS turbo decoder using the SOVA algorithm. Two models are included: - a MyHDL model, along with a…
Ultimate CRC is a CRC generator/checker. Using generics the core can be fully customized. It creates a function of the data input and the CRC…
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