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Core1990 is a point-to-point communication protocol using the royalty-free Interlaken protocol as its foundation. It is designed by engineers and…
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This is another UART project, but is different because that it is very small and will occupy less macrocells on a CPLD. The purpose of this core is…
Please download source code from: https://github.com/linuxbestlzs
VHDL implementation of a UDP/IP core! Area-optimized for direct PC-FPGA communication! An advanced/versatile version of the core is included in the…
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This project, written in generic synthesizable VHDL, provides two separate cores for encoding and decoding byte data according to the 8b/10b…
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please check the source code from: https://github.com/linuxbestahci https://github.com/linuxbestahci_mpi
DQPSK symbol mapper suitable for TETRA/APCO-25 physical layer.
Control the activity and status of your FPGA by targeting a memory mapped space inside it. Based on: -- elements from the GH libraries…
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This project contains a collection of cores that interface with various gamepads. Each gamepad type has a dedicated controller core which handles…
Project content: trunk/vhdl - source of this open core trunk/prototype_1 - example prototype using the GPIB core trunk/prototype_1/fpga - xilinx…
VHDL implementation of the physical layer of the IEEE 802.15.4 standard (TX, RX). The doc/ directory of the repository contains the thesis related…
Open Peer to Peer Interface, Wishbone to Aurora Bridge (OP2P). This interface logic has been designed to provide a very high performance multi-lane…
I2S is an industry standard (invented by Philips) 3-wire interface for streaming stereo audio between devices. Typical applications include digital…
Main features of latest v5 HW are: -LPC memory read (can be disabled),LPC Firmware Hub memory read and IO write for POST Code capture (and display…
I2S to Paralell ADC/DAC controller This provides a bridge between a paralell device (such as a microcontroller (uC) and an I2S (!not! I2C) audio…
I2S to Parallel Interface This module provides a bridge between an I2S serial device (audio ADC, S/PDIF Decoded data) and a parallel device…
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