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Category: DSP Core IP Cores (26)

LinkRunCCA : Linked List & Run-length-based Techniques

LinkRunCCA : Linked List & Run-length-based Techniques

LinkRunCCA is a real-time single-pass connected component analysis/ connected component labeling (CCA/CCL) implemented in Verilog HDL. It can be…

License : LGPL
Language : Verilog
Canny Edge Detector with 9x9 Mask

Canny Edge Detector with 9x9 Mask

Canny edge detector with a 9x9 mask (gradient + gaussian filtering with sigma = sqrt(2)). Able to produce a throughput of 1 pixel per clock cycle.…

License : LGPL
Language : VHDL
Wishbone DSP Compatible Cores

Wishbone DSP Compatible Cores

WDSP project includes three System on Chip (SoC) cores, which implement the Digital Signal Processing (DSP) functions: Finite Impulse Response…

License : LGPL
Language : VHDL
All-pole Lowpass IIR Filters

All-pole Lowpass IIR Filters

The circuits found here implement digital leapfrog filters as described in <http://en.wikibooks.org/wiki/Signal_ProcessingDigital_Filters>.…

License : LGPL
Language : VHDL
Fixed-Point Cascaded FIR Filter

Fixed-Point Cascaded FIR Filter

FIR filter - architecture written with pure verilog - parameterizable in verilog code - cascaded - processing is paralleled - data and coefficients…

License : LGPL
Language : Verilog
Hogenauer Pruning CIC Filter

Hogenauer Pruning CIC Filter

CIC filter It is the CIC filter with Hogenauer pruning. This project is based on https://opencores.org/projects/cic_core project. Differences are…

License : LGPL
Language : Verilog
Cascaded Integrator-comb (CIC) Digital Filter Core

Cascaded Integrator-comb (CIC) Digital Filter Core

Cascaded integrator-comb (CIC) digital filters are computationally efficient implementations of narrowband lowpass filters and are often embedded…

License : LGPL
Language : Other
Fully Pipelined DDS Synthesizer or NCO

Fully Pipelined DDS Synthesizer or NCO

The DDS IP core (dds_synthesizer) is a implementation of a direct digital frequency synthesizer (DDS) (also called number controlled oscillator,…

License : LGPL
Language : VHDL
Dynamic Resizable Streaming FFT2

Dynamic Resizable Streaming FFT2

Integer streaming FFT fixed size and resizable. Language - SystemVerilog. Generator of rotation coefficients in MatLab. Includes Quartus project…

License : LGPL
Language : Verilog
Fast Fourier Transformer (FFT) based FIR Filter

Fast Fourier Transformer (FFT) based FIR Filter

FFT-based FIR Filter is a unit to perform the finite impulse responce filter based on the Fast Fourier Transform (FFT). It performs the convolution…

License : LGPL
Language : VHDL
VHDL Parametrizable FIR Filter

VHDL Parametrizable FIR Filter

VHDL Parametrizable FIR Filter Implementation: -Direct Form II -Real format entry for normalized coeficients -Internal fixed-point implementation…

License : LGPL
Language : VHDL
Floating-point FFT/IFFT on Xilinx FPGA Device

Floating-point FFT/IFFT on Xilinx FPGA Device

This project is the special floating-point Fast Fourier transform realization. Floating point representation has only 24 bits and takes into…

License : LGPL
Language : VHDL
Digital Hilbert Transformer for FPGA-based

Digital Hilbert Transformer for FPGA-based

The Hilbert Transform is an important component in communication systems, e.g. for single sideband modulation/demodulation, amplitude and phase…

License : LGPL
Language : VHDL
Generic FIR Filter in RobustVerilog Parser

Generic FIR Filter in RobustVerilog Parser

Generic FIR filter. Builds optimized filter according to number of multipliers, supports serial or parallel architecture. Supports delays in input.…

License : LGPL
Language : Verilog
Flexible and Generic FIR Filter on FPGA

Flexible and Generic FIR Filter on FPGA

This FIR filter is very generic and flexible. It has been tested working on an FPGA, though the existing version does not yet have a Wishbone…

License : LGPL
Language : VHDL
Low-pass Filter on FIR Linear-phase Structure

Low-pass Filter on FIR Linear-phase Structure

Low-pass filter using an FIR Linear-phase structure for more information please view README file.

License : LGPL
Language : Verilog
Low Power FIR Filter in VHDL Usind OrCAD’s Capture CIS

Low Power FIR Filter in VHDL Usind OrCAD’s Capture CIS

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : VHDL
Fully Pipelined Low-Pass IIR Filter

Fully Pipelined Low-Pass IIR Filter

Low-Pass IIR Filter IP core is a unit to perform the Infinite Impulse Responce (IIR) low pass filter which pass frequency is tuned dynamically Main…

License : LGPL
Language : VHDL
Digital PID Controller - Digital Proportional Integral Derivative Controller Algorithm

Digital PID Controller - Digital Proportional Integral Derivative Controller Algorithm

The PID controller IP core performs digital proportional–integral–derivative controller (PID controller) algorithm. The algorithm first…

License : LGPL
Language : Verilog
Pipelined FFT/IFFT 128 Points Processor

Pipelined FFT/IFFT 128 Points Processor

Pipelined FFT/IFFT 128 points IP core is a unit to perform the Fast Fourier Transform (FFT). It performs one dimensional 128 – complex point…

License : LGPL
Language : Verilog