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Category: Processor IP Cores (91)

OpenRISC 1000 Architecture 32/64-bit RISC/DSP

OpenRISC 1000 Architecture 32/64-bit RISC/DSP

Introduction The aim of the OpenRISC project is to create a free, open source computing platform available under the GNU (L)GPL license. Platform…

License : LGPL
Language : Verilog
AltOr32 - Alternative Lightweight OpenRisc CPU

AltOr32 - Alternative Lightweight OpenRisc CPU

AltOR32 is an OpenRISC 1000 architecture derived RISC CPU targeted at small FPGAs and contains only the most basic ISA features from the OpenRisc…

License : LGPL
Language : Verilog
32-bit FORTH processor with Java compiler on Xilinx

32-bit FORTH processor with Java compiler on Xilinx

A 32-bit FORTH processor conforming to the DPANS'94. This processor was developed as diploma thesis to obtain the academic degree…

License : LGPL
Language : VHDL
16-bit Classical CPU Based Loosely on Caxton Foster’s Blue CPU

16-bit Classical CPU Based Loosely on Caxton Foster’s Blue CPU

A 16-bit classical CPU based loosely on Caxton Foster's Blue CPU from the book "Computer Architecture". Includes a cross assembler…

License : LGPL
Language : Verilog
16 Bit Microcontroller VHDL Assembler

16 Bit Microcontroller VHDL Assembler

Features 800 Xilinx slices for CPU 1000 Xililinx slices for complete SoC Optimized for exeution of C programs VHDL, Assembler, C Compiler,…

License : LGPL
Language : VHDL
16-bit Open uRISC Core Processor

16-bit Open uRISC Core Processor

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : VHDL
Simple RISC 32-bit Pipelined Processor

Simple RISC 32-bit Pipelined Processor

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : Verilog
MC6809/HD6309 Compatible Core Processor

MC6809/HD6309 Compatible Core Processor

A verilog, vendor independent, no cycle accurate MC6809/HD6309 compatible processor core. Goals: - Execute all implemented opcodes - Allow…

License : LGPL
Language : Verilog
A-Z80 CPU - Implementation of the Venerable Zilog Z80 Processor

A-Z80 CPU - Implementation of the Venerable Zilog Z80 Processor

Update: Rewritten in pure Verilog, the CPU can now be used on both Altera and Xilinx devices! A-Z80 is a conceptual implementation of the venerable…

License : LGPL
Language : Verilog
i650 - Verilog RTL Implementation of the Venerable IBM 650 Computer

i650 - Verilog RTL Implementation of the Venerable IBM 650 Computer

A Verilog RTL implementation of the venerable IBM 650 computer. The goal of this project is to use available source materials to recreate a 650 as…

License : LGPL
Language : Verilog
Synthesizable VHDL 8-bit Microcontroller with Extended Peripheral Set

Synthesizable VHDL 8-bit Microcontroller with Extended Peripheral Set

The goal of this project is to create a very well documented, fully synthesizable VHDL model of an 8-bit microcontroller with extended peripheral…

License : LGPL
Language : VHDL
8-bit Pipelined Processor

8-bit Pipelined Processor

n/a

License : LGPL
Language : C/C++
MIPS32 Release 1 - 32-bit MIPS Bare-metal CPU Processor

MIPS32 Release 1 - 32-bit MIPS Bare-metal CPU Processor

UPDATE 1-Jan-2014: This project has moved to GitHub. Please visit https://github.com/granteamips32r1 for the latest code. No further changes will…

License : LGPL
Language : Verilog
AE18 - Clean Room Implementation of Microchip PIC18 Series

AE18 - Clean Room Implementation of Microchip PIC18 Series

The AE18 is a clean room implementation of the Microchip PIC18 series CPU core using information from the PIC18C documentation from their website.…

License : LGPL
Language : Verilog
aeMB - EDK3.2 Clean Room Implementation Microblaze Core Compatible

aeMB - EDK3.2 Clean Room Implementation Microblaze Core Compatible

The aeMB is a clean room implementation of the EDK3.2 compatible Microblaze core using information from the Internet. It is cycle and instruction…

License : LGPL
Language : Verilog
Enhanced MIPS based on MIPS789 Opencores Project

Enhanced MIPS based on MIPS789 Opencores Project

This project is based on MIPS789 opencores project.We used MIPS789 core and added the cache infrastracture and AMBA bus from LEON3.The final core…

License : LGPL
Language : Verilog & VHDL
Alwcpu - 16-bit light weight CPU

Alwcpu - 16-bit light weight CPU

Alwcpu is a light weight CPU in terms of logic resources. - 16 bit address and data bus. (Instructions are 16 bit as well) - Wishbone interface -…

License : LGPL
Language : VHDL
Amber ARM-compatible 32-bit RISC Core Processor

Amber ARM-compatible 32-bit RISC Core Processor

The Amber processor core is an ARM-compatible 32-bit RISC processor. The Amber core is fully compatible with the ARM® v2a instruction set…

License : LGPL
Language : Verilog
An Inventory Of Soft Processor Cores

An Inventory Of Soft Processor Cores

Other project properties Category:Processor Language:Verilog & VHDL Development status:Alpha Additional info: WishBone compliant: No WishBone…

License : LGPL
Language : Verilog & VHDL
copyBlaze - Synthesizable VHDL Clone 8bit PicoBlaze Embedded Microcontroller

copyBlaze - Synthesizable VHDL Clone 8bit PicoBlaze Embedded Microcontroller

copyBlaze is a from-scratch synthesizable & behavioral VHDL clone of Ken Chapman's popular 8bit PicoBlaze embedded microcontroller. It…

License : LGPL
Language : VHDL