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CMOS Logic Gates
27 questions By Tony R. Kuphaldt
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Question 13 of 27
In high-speed digital circuits, a very important logic gate parameter is propagation delay: the delay time between a change-of-state on a gate’s input and the corresponding change-of-state on that gate’s output. Consult a manufacturer’s datasheet for any CMOS logic gate and report the typical propagation delay times published there.
Also, explain what causes propagation delay in logic gates. Why isn’t the change in output state instantaneous when an input changes states?
Reveal answerI’ll leave the research of specific propagation time delay figures up to you! The reason propagation delay exists is because transistors cannot turn on and turn off instantaneously. In insulated-gate field-effect transistors, this is primarily due to the time required to charge or discharge the gate-to-channel capacitance.
Follow-up questions: What difference is there between high-to-low output transitions versus low-to-high output transitions for the gate you researched? Which transition is faster?
Notes:I purposely omitted answers for this question, not only because I want students to do the research on their own, but also because it makes it more interesting when students consult different datasheets and derive different answers (for different logic “families”)!
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Question 14 of 27
Logic gates are limited in the number of gate inputs which one output can reliably drive. This limit is referred to as fan-out:
Explain why this limit exists. What is it about the construction of CMOS logic gates that inherently limits the number of CMOS inputs that any one CMOS output can drive? What might happen if this limit is exceeded?
Fan-out for CMOS is a quite different than fan-out for TTL. Most importantly is that CMOS fan-out is inversely proportional to operating frequency. Explain why.
Reveal answerA fan-out limit for CMOS exists because CMOS outputs have to source and sink capacitive charging and discharging current from the CMOS inputs. I’ll let you determine why this limit is frequency-dependent.
Notes:For the relatively simple digital circuits that beginning students build, fan-out is rarely a problem. More likely is that students will try to drive a load that is too “heavy,” causing the same voltage level problem.
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Question 15 of 27
An important parameter of logic gate circuitry is noise margin. What exactly is “noise margin,” and how is it defined for logic gates?
Specifically, how much noise margin do digital circuits exclusively composed of CMOS gates have? How does this compare with the noise margin of all-TTL circuitry?
Note: you will need to consult CMOS gate datasheets to answer this question properly.
Reveal answerNoise margin is the difference between the acceptable voltage limits for corresponding input and output logic states.
Notes:This question, to be answered properly, involves more than just a definition of “noise margin.” Students must first discover that there is a difference between voltage compliance levels for gate inputs versus outputs, then recognize that the difference constitutes a “margin” that imposed AC voltage (“noise”) must not exceed. They must then present their answer in terms of manufacturer specifications, obtained in datasheets. In summary, there is a lot of research that must occur to answer this question, but the results will be worth it!
