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CMOS Logic Gates
27 questions By Tony R. Kuphaldt
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Question 25 of 27
What logic state does a floating CMOS gate input naturally assume? How does this compare against traditional TTL?
Reveal answerA floating CMOS gate does not assume any definite logic state! The logic state of a floating CMOS gate input is indeterminate.
Follow-up question: what state does a floating input assume for a high-speed CMOS (74HCxx) logic gate, which is designed to be an upgrade/replacement for traditional TTL gates?
Notes:Ask your students to explain their answer based on an analysis of the internals of a CMOS gate, versus the internals of a TTL gate. Memorization is not good enough - students must grasp why these different logic families behave as they do.
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Question 26 of 27
As an electronics instructor, I have the opportunity to see a lot of creative mistakes made by students as they learn to build circuits. One very common mistake made in CMOS circuit construction manifests itself in erratic behavior: the circuit may function correctly for a time, but suddenly and randomly it stops. Then, just by waving your hand next to the circuit, it begins to work again!
This problem is especially prevalent on days where the atmospheric humidity is low, and static electric charges easily accumulate on objects and people. Explain what sort of CMOS wiring mistake would cause a powered logic gate to behave erratically due to nearby static electric fields, and what the proper solution is to this problem.
Reveal answerThis classic problem is caused by a lack of pullup or pulldown resistors on CMOS gate inputs.
Notes:Students think I’m a wizard by being able to troubleshoot their CMOS circuits just by waving my hand next to them. No, I’m just wise in the ways of common student error!
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Question 27 of 27
Logic probes are useful tools for troubleshooting digital logic gate circuits, but they certainly have limitations. For instance, in this simple circuit, a logic probe will give correct “high” and “low” readings at test point 1 (TP1), but it will always read “low” (even when the LED is on) at test point 2 (TP2):
Now, obviously the output of the gate is “high” when the LED is on, otherwise it would not receive enough voltage to illuminate. Why then does a logic probe fail to indicate a high logic state at TP2?
Reveal answerI won’t give away the answer here, but it has something to do with proper CMOS logic level voltages.
Follow-up question: this LED circuit is rather simple, and the scenario almost silly, because the LED’s presence makes checking the logic state at TP1 and TP2 superfluous! Can you think of any other circuit or situation where a similar false reading may be displayed by a logic probe - where the logic state has not been made visually obvious by the presence of an LED?
Notes:It is easy for students to overlook the limitations of a logic probe, and to forget what actually drives it to say “high” or “low” when measuring a logic level. This is why in low-speed circuits I prefer to use a good digital voltmeter rather than a logic probe to discern logic states. With a voltmeter, you can see exactly what the voltage level is, and determine whether or not the logic state is marginal.
